ADDRESS

Cadence Design Systems, Inc.
555 River Oaks Parkway, Bldg 2, MS 2B1
San Jose, CA 95134
(408)-576-3586

UNIVERSITY OF CALIFORNIA, LOS ANGELES

Ph. D. candidate in Computer Science (starting September 1997)

CARNEGIE MELLON UNIVERSITY

Master of Science in Computer Science, 1995
Specialization: VLSI Computer-Aided Design, Formal Hardware Verification

Course Work (graduate level): Computer Network, Programming Parallel Algorithms, Computer Systems, Programming Languages, Algorithms, Artificial Intelligence, Operating Systems, Verification of Real-Time, and Reactive System

UNIVERSITY OF CALIFORNIA, LOS ANGELES

Bachelor of Science, graudated Summa Cum Laude
Major: Computer Science and Engineering (GPA 4.0)

Course Work: Physical Design Automation of VLSI Systems (graduate level), Independent Studies, Computer Network Architectures, Database Design, Principle of Compiler Design, System Modeling, Operating Systems, Computer Architectures, Systems Programming, Electronics, Digital Integrated Circuits, Artificial Intelligence, Automata Theory, Programming Languages, Artificial Intelligence, Applied Numerical Methods, and Systems and Signals

• Nominee, IEEE Transaction on CAD Best Paper Award, 1996
  
• Recipient, CMU Graduate Fellowship, 1993 - present
  
• Recipient, UCLA School of Engineering Outstanding Bachelor Award, 1993
  
• Recipient, UCLA Computer Science Department Outstanding Senior Award, 1993
  
• Second Prize Winner, IEEE National Programming Contest, 1993
  
• Recipient, NSF Undergraduate Research Experience Grant, 1992
  
• Recipient, UCLA President's Undergraduate Fellowship, 1992
  
• Fourth Prize Winner, Internet Programming Contest, 1992
  
• Third Prize Winner, ACM Regional Scholastic Programming Contest, 1992
  
• Recipient, Golden Key - Peat Warwick Scholarship, 1992
  
• Member, Golden Key National Honor Society, 1992
  
• Member, Tau Beta Pi Engineering Honor Society, 1991
  
• Recipient, UCLA School of Engineering
• Dean's Honor List, 1990 - 1993
  
• Member, Alpha Lambda Delta (National Freshman Honor Society), 1990
  
• Member, Phi Eta Sigma (National Freshman Honor Society), 1990
  
• First Prize Winner, International Mathematical Olympiad HK Contest, 1989
  

May 1994 - August 1994

Summer Intern, Intel SSD
Research in the area of circuit partitioning and parallel circuit simulation. Projects included porting the COSMOS switch-level simulation package to PARAGON, and developing a latch-boundary partitioning algorithm for PARAGON and FPGA-based hardware simulation.

June 1993 - August 1993

Summer Intern, AT&T Bell Laboratories
Integrated and developed new performance-driven layout packages for full-customed designs.

April 1992 - June 1993

Undergraduate Research Assistant, UCLA
Developed efficient and high-performance routing and wiresizing algorithms for computer-aided designs of VLSI circuits.

OTHER EXPERIENCE

April 1992 - March 1993

MicroMouse Design Team Member, UCLA
Developed software-hardware interfaces and high level maze exploration algorithms as a part of an ongoing UCLA MicroMouse Design Project.

June 1991 - September 1991

International Advisor, Office of International Students and Scholars, UCLA
Organized programs and activities to introduce new foreign students to the community. Learned communication, managerial, and leadership skills.

ADDITIONAL SKILLS

Programming Languages: C++, C, Java, HTML, Pascal, Ada, Lisp, Scheme, NESL, BASIC, VHDL, Fortran, postscript, and various assembly languages and UNIX shells.

Environments: Unix (SunOS, Solaris, HP/UX, Ultrix, and AIX), MacOS, PARAGON OSF, DOS, X Windows, and MS Windows.

Other Tools: Purify, Quantify, RCS/SCCS, SNiFF+, SMV, COSMOS, SPICE, Tcl/Tk, LaTeX, Framemaker, LEDA, Expect, Maple, Emacs, VI, GDB, XDB, dbx, softbench, YACC, Lex, AWK, PERL, SED, WorkView, MS Excel, WordPerfect, and MS Word.

Reviewer, IEEE International Symposium on Circuits and Systems, 1996 - present
Reviewer, IEEE/ACM International Conference on Computer Aided Design, 1996 - present
Reviewer, ACM Transaction on Design Automation of Electronic Systems, 1995 - present
Reviewer, Design Automation Conference, 1992 - present
Student Member, Association for Computing Machinery, 1992 - 1996
Member, UCLA International Student Association, 1990 - 1993
Participant, UCLA Cross Cultural Contact, 1991
Table tennis, racketball, chess, shogi, war games, and computer graphics.

JOURNAL PAPERS

`` Efficient Algorithms for the Minimum Shortest Path Steiner Arborescence Problem with Applications to VLSI Physical Design'', submitted to IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, 1998 (with J. Cong and A. B. Kahng ) (invited submission).

`` Fast Optimal Algorithms for the Minimum Rectilinear Steiner Arborescence Problem'', submitted to Algorithmica, 1997 (with J. Cong ).

``Optimal Wiresizing Under the Distributed Elmore Delay Model'' IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, 3(1995), pp. 321 - 336 (with J. Cong ) (nominated for IEEE Transaction on CAD Best Paper Award, 1996).

`` Fast Optimal Algorithms for the Minimum Rectilinear Steiner Arborescence Problem'', Int'l Symposium on Circuits and Systems, 1997, to appear (with J. Cong ) (slides are also available).

`` Efficient Heuristics for the Minimum Shortest Path Steiner Arborescence Problem with Applications to VLSI Physical Design'', Int'l Symposium on Physical Design, 1997, pp. 88 - 95 (with J. Cong and A. B. Kahng ) (slides are also available).

``Simultaneous Buffer and Wire Sizing for Performance and Power Optimization'' Int'l Symposium on Low Power Electronics and Design, 1996, pp. 271 - 276 (with J. Cong and C. K. Koh ).

``Fast Simulation: Using Intel Architecture Servers to Beat Hardware Accelerators'', Intel Design and Test Technology Conference, 1995 (with J. Casas, M. Joshi, M. Khaira, S. Otto, E. Seligman, S. H. Teng , and H. H. Yang).

``Wiresizing with Driver Sizing for for Performance and Power Optimization'', Int'l Workshop on Low Power Design, 1994, pp. 81 - 86 (with J. Cong and C. K. Koh ).

``Optimal Wiresizing Under the Distructed Elmore Delay Model'', Int'l Conference on Computer-Aided Design, 1993, pp. 110 - 114 (with J. Cong ) (slides are also available).

``Performance Driven Interconnect Design based on Distributed RC Delay Model'', Design Automation Conference, 1993, pp. 606 - 611 (with J. Cong and D. Zhou ) (slides are also available).

``On High-Speed VLSI Interconnects: Analysis and Design'', Asia-Pacific Conference on Circuits and Systems, 1992, pp. 35 - 40 (with K. D. Boese , J. Cong , A. B. Kahng , D. Zhou ) (invited paper) (slides are also available).

``PDAR Detailed Router'', Intel Design and Test Technology Conference, 1996 (with M. K. Mohan and G. Suto).

``Performance Driven Interconnect Design based on Distributed RC Delay Model'', UCLA Computer Science Department Annual Research Review, 1993 (with J. Cong and D. Zhou ) (slides are also available).

``Fast Optimal Algorithms for the Minimum Rectilinear Steiner Arborescence Problem'', UCLA-CSD-960037, 1996 (with J. Cong ).

``On the Construction of Optimal or Near-Optimal Steiner Arborescence'', UCLA-CSD-960033, 1996 (with J. Cong ).

``Optimal Wiresizing Under the Distructed Elmore Delay Model'', UCLA-CSD-930012, 1993 (with J. Cong ).

``Performance Driven Interconnect Design based on Distributed RC Delay Model'', UCLA-CSD-920043, 1992 (with J. Cong ) and D. Zhou ).

``Fast Optimal Algorithms for the Minimum Steiner Arborescence Problem in General Graph'' (with J. Cong ).

``A Class of Heuristics for the Rectilinear Steiner Arborescence with Good Performance'' (with J. Cong ).

``Improved Exact Algorithm for Constructing Rectilinear Steiner Trees on a Checkerboard'' (with J. Cong ).