Session 2 Design of UltraSPARC
Chair: Nigel Ross
Session 3 Power Considerations in Synthesis
Chair: Jan Rabaey
Session 4 Technology and Layout Dependent Synthesis
Chair: Gabriele Saucier
Session 5 Issues in EDA Frameworks
Chair: Ken Slater
Session 6 Panel: Managing Design Change - Lessons Learned
Chair: Donald Reinertsen
Panelists: Franz Fink, John Lods, Thomas P. Pennino, Dave Rollenhagen
Session 7 Scheduling and Retiming in Architectural Synthesis
Chair: David Ku
Session 8 Delay Test and Diagnosis
Chair: Peter C. Maxwell
Session 9 Discrete-Event Simulation
Chair: Peter M. Maurer
Session 10 Panel: Power Minimization in IC Design
Chair: Massoud Pedram
Panelists: Walter Davis, Adel Khouja, Uming Ko, Raymond Leung, Simon Napper, Stefaan Note, Jan Rabaey
Session 11 Storage Synthesis and Optimization
Chair: F. Kurdahi
Session 12 Retiming and Sequential ATPG
Chair: Sandip Kundu
Session 13 Partitioning and Placement
Chair: Antun Domic
Session 14 Design Case Studies
Chair: Scott Nance
Session 15 Panel: University-Industry Ties: How Can They Be Improved?
Chair: Randal E. Bryant
Panelists: Richard Bushroe, John Darringer, Daniel D. Gajski, Robert Hum, Tokinori Kozawa, Alberto L. Sangiovanni-Vincentelli, John Toole
Session 16 Low Power Design
Chair: Suresh Rajgopal
Sasan Iman, Massoud Pedram
Session 17 Extraction and Module Generation
Chair: Youn-Long Lin
Session 18 Advanced Methods in Practice
Chair: Don Stark
Session 19 Sequential Logic Synthesis
Chair: Narendra Shenoy
Session 20 Fault Modeling and Simulation
Chair: M. Ray Mercer
Session 21 CAD for Interconnect
Chair: Andrzej J. Strojwas
Session 22 Tutorial: ASIC Prototyping
Chair: Gabriele Saucier
Presenters: Jack Donovan, Haz Nabulsi, Vincent Olive, Gabriele Saucier,
Ralph Zak
Session 23 Datapath Synthesis and Modeling
Chair: Robert A. Walker
Session 24 Learning and Counterexamples in Formal Verification
Chair: Carl Pixley
Session 25 Analog CAD
Chair: Jacob White
Session 26 Panel: DOS, Windows, UNIX: EDA and the OS Wars
Chair: Richard Goering
Panelists: Brian Moran, David Orecchio, David Pellerin, Jim Plymale, Nigel Ross, Patrick Williams
Session 27 Software Analysis and Synthesis
Chair: Rajesh K. Gupta
Session 28 Electrical Simulation
Chair: Lawrence T. Pileggi
Session 29 Optimization of Clock and Power Distribution
Chair: Jason Cong
Session 30 Concurrent Engineering
Chair: Neil Weste
Session 31 Panel: The ESDA Landscape: Who Will Dominate?
Chair: Kurt Keutzer
Panelists: Moshe Cohen, Dominique Genin, Joachim Kunkle, Jan Rabaey, James Rowson, Gary Smith
Session 32 Formal Verification of Arithmetic Circuits
Chair: Gary D. Hachtel
Session 33 Routing for FPGAs
Chair: Stephen Brown
Session 34 EDA and the WWW
Chair: Sean Murphy
Session 35 Code Generation for Embedded Systems
Chair: Pierre Paulin
Session 36 Switching Activity and Power Analysis
Chair: Farid N. Najm
Session 37 Combinational Logic Synthesis
Chair: Yosinori Watanabe
Session 38 Panel: Deep Submicron Design Challenges
Chair: Mike Smith
Panelists: David Gregory, Jim Hogan, Tsutomu Iio, George Janac, Bill McCaffrey, Scott Nogueira
Session 39 Complexity Measures for VHDL
Chair: Reinaldo A. Bergamaschi
Session 40 Timing Analysis and Optimization
Chair: Ibrahim N. Hajj
Session 41 Asynchronous Synthesis
Chair: Steve Nowick