TABLE OF CONTENTS ICCAD'94

SESSION 1A MULTI-LEVEL LOGIC OPTIMIZATION

1A.1 Perturb and Simplify: Multi-Level Boolean Network Optimizer
Shih-Chieh Chang, M. Marek-Sadowska, Univ. of California, Santa Barbara, CA

1A.2 Multi-Level Logic Optimization by Implication Analysis
Wolfgang Kunz, Univ. of Potsdam, Potsdam, Germany, Prem Menon, Univ. of Massachusetts, Amherst, MA

1A.3 Incremental Synthesis
Daniel Brand, IBM Research Division, Yorktown Heights, NY, Anthony D. Drumm, IBM AS/400 Division, Rochester, MN
Sandip Kundu, IBM Research Division, Yorktown Heights, NY, Prakash Narain, IBM Microelectronics, Endicott, NY

SESSION 1B MEMORY ISSUES IN HIGH-LEVEL SYNTHESIS

1B.1 Definition and Solution of the Memory Packing Problem for Field-Programmable Systems
David Karchmer, Jonathan Rose, Univ. of Toronto, Toronto, Ontario, Canada

1B.2 Integrating Program Transformations in the Memory-Based Synthesis of Image and Video Algorithms
David J. Kolson, Alexandru Nicolau, Nikil Dutt, Univ. of California, Irvine, CA

1B.3 DataFlow-Driven Memory Allocation for Multi-Dimensional Signal Processing Systems
Florin Balasa, Francky Catthoor, Hugo De Man, IMEC, Leuven, Belgium

SESSION 1C TEST GENERATION

1C.1 Test Generation for Bridging Faults in CMOS ICs Based on Current Monitoring Versus Signal Propagation
Uwe Gläser, Theodor Vierhaus, Marco Kley, Anja Wiederhold, GMD, Sankt Augustin, Germany

1C.2 Iterative [Simulation Based Genetics + Deterministic Techniques] = Complete ATPG
Daniel G. Saab, Univ. of Illinois, Urbana, IL, Youssef G. Saab, Univ. of Missouri, Columbia, MO,
Jacob A. Abraham, Univ. of Texas, Austin, TX

1C.3 Analytical Fault Modeling and Static Test Generation for Analog ICs
Giri Devarayanadurg, Mani Soma, Univ. of Washington, Seattle, WA

SESSION 1D PARTITIONING/CLUSTERING

1D.1 Efficient Network Flow Based Min-Cut Balanced Partitioning
Honghua Yang, D.F. Wong, Univ. of Texas, Austin, TX

1D.2 Multi-Way VLSI Circuit Partitioning Based on Dual Net Representation
Jason Cong, Wilburt Labio, Narayanan Shivakumar, Univ. of California, Los Angeles, CA

1D.3 A General Framework for Vertex Orderings, with Applications to Netlist Clustering
Charles J. Alpert, Andrew B. Kahng, Univ. of California, Los Angeles, CA

SESSION 2A SEQUENTIAL SYNTHESIS FOR LOW POWER

2A.1 Re-Encoding Sequential Circuits to Reduce Power Dissipation
Gary D. Hachtel, Mariano Hermida, Abelardo Pardo, Massimo Poncino, Fabio Somenzi, Univ. of Colorado, Boulder, CO

2A.2 Precomputation-Based Sequential Logic Optimization for Low Power
Mazhar Alidina, José Monteiro, Srinivas Devadas, Massachusettes Inst. of Tech., Cambridge, MA,
Abhijit Ghosh, Mitsubishi Electronics, Sunnyvale, CA, Marios Papaefthymiou, Yale Univ., New Haven, CT

2A.3 Low Power State Assignment Targeting Two-And Multi-Level Logic Implementations
Chi-ying Tsui, Massoud Pedram, Chih-ang Chen, Alvin Despain, Univ. of Southern California, Los Angeles, CA

SESSION 2B SYSTEM OPTIMIZATION, PARTITIONING, AND INTEGRATION

2B.1 Algorithm Selection: A Quantitative Computation-Intensive Optimization Approach
Miodrag Potkonjak, NEC USA, C&C Research Labs., Princeton, NJ, Jan Rabaey, Univ. of California, Berkeley, CA

2B.2 Adaptation of Partitioning and High-Level Synthesis in Hardware/Software Co-Synthesis
Jörg Henkel, Rolf Ernst, Ulrich Holtmann, Thomas Benner, Technische Univ. Braunschweig, Braunschweig, Germany

2B.3 Synthesis of Concurrent System Interface Modules with Automatic Protocol Conversion Generation
Bill Lin, Steven Vercauteren, IMEC, Leuven, Belgium

SESSION 2C BUILT-IN SELF-TEST

2C.1 An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures
Sybille Hellebrand, Hans-J. Wunderlich, Univ. of Siegen, Siegen, Germany

2C.2 Test Pattern Generation Based on Arithmetic Operations
Sanjay Gupta, Janusz Rajski, Jerzy Tyszer, McGill Univ., Montréal, Quebec, Canada

2C.3 Random Pattern Testable Logic Synthesis
Chen-Huan Chiang, Sandeep Gupta, Univ. of Southern California, Los Angeles, CA

SESSION 2D PLACEMENT

2D.1 Compression-Relaxation: A New Approach to Performance Driven Placement for Regular Architectures
Anmol Mathur, C. L. Liu, Univ. of Illinois, Urbana, IL

2D.2 A Loosely Coupled Parallel Algorithm for Standard Cell Placement
Wern-Jieh Sun, Carl Sechen, Univ. of Washington, Seattle, WA

2D.3 Delay and Area Optimization for Compact Placement by Gate Resizing and Relocation
Weitong Chuang, AT&T Bell Labs., Murray Hill, NJ, Ibrahim N. Hajj, Univ. of Illinois, Urbana, IL

SESSION 3A FPGA SYNTHESIS AND ARCHITECTURE

3A.1 Edge-Map: Optimal Performance Driven Technology Mapping for Iterative Lut Based FPGA Designs
Honghua Yang, D.F. Wong, Univ. of Texas, Austin, TX

3A.2 Maple: A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays
Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki, Waseda Univ., Tokyo, Japan

3A.3 Universal Logic Gate for FPGA Design
Chih-chang Lin, M. Marek-Sadowska, Duane Gatlin, Univ. of California, Santa Barbara, CA

SESSION 3B CONCURRENCY MODELING AND ESTIMATION

3B.1 Condition Graphs for High-Quality Behavioral Synthesis
Hsiao-Ping Juan, Viraphol Chaiyakul, Daniel D. Gajski, Univ. of California, Irvine, CA

3B.2 Dynamic Scheduling and Synchronization Synthesis of Concurrent Digital Systems under System-Level Constraints
Claudionor Nunes Coelho Jr., Giovanni De Micheli, Stanford Univ., Stanford, CA

3B.3 Comprehensive Lower Bound Estimation from Behavioral Descriptions
Seong Y. Ohm, Fadi J. Kurdahi, Nikil Dutt, Univ. of California, Irvine, CA

SESSION 3C TIMING MODELING AND SIMULATION

3C.1 Fast and Accurate Timing Simulation with Regionwise Quadratic Models of MOS I-V Characteristics
A. Dharchoudhury, Sung Mo Kang, Univ. of Illinois, Urbana, IL, K.H. Kim

S.H. Lee, Samsung Electronics Co., Kyung-Ki-Do, Korea

3C.2 VLSI Timing Simulation with Selective Dynamic Regionization
Meng-Lin Yu, Bryan D. Ackland, AT&T Bell Labs., Holmdel, NJ

3C.3 A New Efficient Approach to Statistical Delay Modeling of CMOS Ditigal Combinational Circuits
S. A. Aftab, Motorola Strategis Systems Tech., Temple, AZ, M.A. Styblinski, Texas A&M Univ., College Station, TX

SESSION 3D CLOCK AND ROUTING ALGORITHMS FOR HIGH PERFORMANCE SYSTEMS

3D.1 Simultaneous Driver and Wire Sizing for Performance and Power Optimization
Jason Cong, Cheng-Kok Koh, Univ. of California, Los Angeles, CA

3D.2 Low-Cost Single Layer Clock Trees with Exact Zero Elmore Delay Skew
Andrew B. Kahng, C.-W Albert Tsao, Univ. of California, Los Angeles, CA

3D.3 Clock-Period Constrained Minimal Buffer Insertion in Clock Trees
Gustavo E. Téllez, Majid Sarrafzadeh, Northwestern Univ., Evanston, IL

SESSION 4A RETIMING AND SEQUENTIAL TECHNOLOGY MAPPING

4A.1 Efficient Implementation of Retiming
Narendra Shenoy, Richard Rudell, Synopsys, Inc., Mountain View, CA

4A.2 Retiming with Non-Zero Clock Skew, Variable Register, and Interconnect Delay
Tolga Soyata, Eby G. Friedman, Univ. of Rochester, Rochester, NY

4A.3 Optimal Latch Mapping and Retiming Within a Tree
Joel Grodstein, Eric Lehman, Heather Harkness, Bill Grundmann, Herve Touati, Digital Equipment Corp., Hudson, MA

SESSION 4B ISSUES IN DISCRETE SIMULATION

4B.1 Simulation of Digital Circuits in the Presence of Uncertainty
Mark Linderman, Miriam Leeser, Cornell Univ., Ithaca, NY

4B.2 Fast Transient Power and Noise Estimation for CMOS VLSI Circuits
Wolfgang T. Eisenmann, Motorola GmbH, Munich, Germany
Helmut E. Graeb, Technical Univ. of Munich, Munich, Germany

4B.3 The Inversion Algorithm for Digital Simulation
Peter Maurer, Univ. of South Florida, Tampa, FL

SESSION 4C TECHNOLOGY CAD

4C.1 Unified Complete Mosfet Model for Analysis of Digital and Analog Circuits
M. Miura-Mattausch, U. Feldmann, A. Rahm, M. Bollu, D. Savignac, Siemens AG, Munich, Germany

4C.2 A Precorrected-FFT Method for Capacitance Extraction of Complicated 3-D Structures
J.R. Phillips, J. White, Massachusetts Inst. of Tech., Cambridge, MA

4C.3 Measurement and Modeling of MOS Transistor Current Mismatch in Analog IC's
Eric Felt, Amit Narayan, Alberto-Sangiovanni-Vincentelli, Univ. of California, Berkeley, CA

SESSION 4D MINIMIZING CLOCK SKEW

4D.1 Skew Sensitivity Minimization of Buffered Clock Tree
Jae Chung, Chung-Kuan Cheng, Univ. of California, La Jolla, CA

4D.2 Process-Variation-Tolerant Clock Skew Minimization
Shen Lin, C.K. Wong, IBM Corp., Yorktown Heights, NY

4D.3 A Specified Delay Accomplishing Clock Router Using Multiple Layers
Mitsuho Seki, Kenji Inoue, Hitachi, Ltd., Ibaraki-ken, Japan

Kazuo Kato, Kouki Tsurusaki, Shinichi Fukasawa, Hitoshi Sasaki, Mutsuhito Aizawa, Hitachi, Ltd., Tokyo, Japan

SESSION 5A ESTIMATION TECHNIQUES FOR POWER CONSUMPTION

5A.1 Switching Activity Analysis Considering Spatiotemporal Correlations
Radu Marculescu, Diana Marculescu, Massoud Pedram, Univ. of Southern California, Los Angeles, CA

5A.2 Estimation of Circuit Activity Considering Signal Correlations and Simultaneous Switching
Tan-Li Chou, Kaushik Roy, Purdue Univ., West Lafayette, IN, Sharat Prasad, Texas Instrments Inc., Dallas, TX

5A.3 A Cell-Based Power Estimation in CMOS Combinational Circuits
Jiing-Yuan Lin, T.C. Liu, Wen-Zen Shen, National Chiao Tung Univ., Hsin-chu, Taiwan, ROC

SESSION 5B RESOURCE BINDING

5B.1 Design Exploration for High-Performance Pipelines
Smita Bakshi, Daniel D. Gajski, Univ. of California, Irvine, CA

5B.2 Simultaneous Functional-Unit Binding and Floorplanning
Yung-ming Fang, D.F. Wong, Univ. of Texas, Austin, TX

5B.3 Module Selection and Data Format Conversion for Cost-Optimal DSP Synthesis
Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi, Univ. of Minnesota, Minneapolis, MN

SESSION 5C DELAY AND ANALOG TESTING

5C.1 On Testing Delay Faults in Macro-Based Combinational Circuits
Irith Pomeranz, Sudhakar Reddy, Univ. of Iowa, Iowa City, IA

5C.2 RAFT: A Novel Program for Rapid-Fire Test and Diagnosis of Digital Logic for Marginal Delays and Delay Faults
Abhijit Chatterjee, Georgia Inst. of Tech., Atlanta, GA, Jacob A. Abraham, Univ. of Texas, Austin, TX

5C.3 A Comprehensive Fault Macromodel for OPAMPS
Chen-Yang Pan, Kwang-Ting Cheng, Univ. of California, Santa Barbara, CA
Sandeep Gupta, Univ. of Southern California, Los Angeles, CA

SESSION 5D ROUTING FOR FPGAS

5D.1 A Channel-Driven Global Routing with Consistent Placement
Shigetoshi Nakatake, Yoji Kajitani, JAIST, Ishikawa, Japan

5D.2 A New Global Routing Algorithm for FPGAs
Yao-Wen Chang, S. Thakur, K. Zhu, D.F. Wong, Univ. of Texas, Austin, TX

5D.3 On the NP-Completeness of Regular 2-D FPGA Routing Architectures and a Novel Solution
Yu-Liang Wu, Douglas Chang, Univ. of California, Santa Barbara, CA

SESSION 6A OPTIMIZATION FOR LOW POWER

6A.1 A Symbolic Method to Reduce Power Consumption of Circuits Containing False Paths
R. Iris Bahar, Gary D. Hachtel, Enrico Macii, Fabio Somenzi, Univ. of Colorado, Boulder, CO

6A.2 Multi-Level Network Optimization Targeting Low Power
Sasan Iman, Massoud Pedram , Univ. of Southern California, Los Angeles, CA

6A.3 LP Based Cell Selection with Constraints of Timing, Area and Power Consumption
Yutaka Tamiya, Yusuke Matsunaga, Fujitsu Labs. Ltd., Kawasaki, Japan
Masahiro Fujita, Fujitsu Laboratories of America, San Jose, CA

SESSION 6B EMBEDDED SOFTWARE

6B.1 Power Analysis of Embedded Software: A First Step Towards Software Power Minimization
Vivek Tiwari, Sharad Malik, Andrew Wolfe, Princeton Univ., Princeton, NJ

6B.2 Generating Instruction Sets and Microarchitectures from Applications
Ing-Jer Huang, Alvin Despain, Univ. of Southern California, Los Angeles, CA

6B.3 Register Assignment Through Resource Classification for ASIP Microcode Generation
Clifford Liem, Trevor May, Pierre Paulin, Bell-Northern Research Inc., Ottawa, Ontario, Canada

SESSION 6C PADE BASED CIRCUIT AND INTERCONNECT ANALYSIS

6C.1 Efficient Small-Signal Circuit Analysis and Sensitivity Computations with the PVL Algorithm
Roland W. Freund, Peter Feldmann, AT&T Bell Labs., Murray Hill, NJ

6C.2 Capturing Time-Of-Flight Delay for Transient Analysis Based on Scattering Parameter Macromodel
Haifang Liao, Wayne W.M. Dai, Univ. of California, Santa Cruz, CA

6C.3 RC Interconnect Synthesis - A Moment Fitting Approach
Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage, Univ. of Texas, Austin, TX

SESSION 6D FLOORPLANNING

6D.1 Adaptive Cut Line Selection in Min-Cut Placement for Large Scale Sea-of-Gates Arrays
Kazuhiro Takahashi, Mitsubishi Electric Corp., Itami Hyogo, Japan, Kazuo Nakajima, Univ. of Maryland, College Park, MD
Masayuki Terai, Koji Sato, Mitsubishi Electric Corp., Itami Hyogo, Japan

6D.2 Folding a Stack of Equal Width Components
Venkat Thanvantri, Sartaj Sahni, Univ. of Florida, Gainesville, FL

6D.3 Area Minimization for Hierarchical Floorplans
Peichen Pan, Univ. of Ilinois, Urbana, IL, Weiping Shi, Univ. of North Texas, Denton, TX, C.L. Liu, Univ. of Illinois, Urbana, IL

SESSION 7A FORMAL VERIFICATION

7A.1 Multi-Level Synthesis for Safe Replaceability
Carl Pixley, Motorola, Inc., Austin. TX, Vigyan Singhai, Adnan Aziz, Robert K. Brayton, Univ. of California, Berkeley, CA

7A.2 Iterative Algorithms for Formal Verification of Embedded Real-Time Systems
Felice Balarin, Alberto Sangiovanni-Vincentelli, Univ. of California, Berkeley, CA

7A.3 Incremental Formal Design Verification
Gitanjali M. Swamy, Robert K. Brayton, Univ. of California, Berkeley, CA

SESSION 7B TIMING OPTIMIZATION BY GATE SIZING

7B.1 Optimization of Critical Paths in Circuits with Level-Sensitve Latches
Timothy M. Burks, IBM Corp., Austin, TX, Karem Sakallah, Univ. of Michigan, Ann Arbor, MI

7B.2 Computing the Entire Active Area/Power Consumption Versus Delay Trade-Off Curve for Gate Sizing with a Piecewise Linear Simulator
Michel Berkelaar, IBM Corp., Yorktown Heights, NY, Pim H.W. Buurman, Jochen A.G. Jess, Eindhoven Univ. of Tech., Eindhoven, The Netherlands

7B.3 Dynamical Identification of Critical Paths for Iterative Gate Sizing How-Rern Lin, Ting-Ting Hwang, Tsing Hua Univ., Hsin-chu, Taiwan, ROC

9C.2 A Statistical Optimization-Based Approach for Automated Sizing of Analog Cells
F. Medeiro, F.V. Fernández, R. Domínguez-Castro, A. Rodríguez-Vázguez, Centro Nacional de Microelectrónica, Sevilla, Spain

9C.3 Time-Domain Non-Monte Carlo Noise Simulation for Nonlinear Dynamic Circuits with Arbitrary Excitations
Alper Demir, Edware Liu, Alberto Sangiovanni-Vincentelli, Univ. of California, Berkeley, CA

SESSION 9D EFFICIENT ROUTING ALGORITHMS

9D.1 Improving Over-The-Cell Channel Routing in Standard Cell Design
Xiaolin Liu, Ioannis G. Tollis, Univ. of Texas, Richardson, TX

9D.2 Minimmum Crosstalk Switchbox Routing
Tong Gao, C.L. Liu, Univ. of Illinois, Urbana, IL

9D.3 Techniques for Crosstalk Avoidance in the Physical Design of High-Performance Deigital Systems
Desmond Kirkpatrick, Alberto Sangiovanni-Vincentelli, Univ. of California, Berkeley, CA

SESSION 10A BDDs and Applications

10A.1 Efficient Breadth-First Manipulation of Binary Decision Diagrams
Pranav Ashar, Matthew Cheong, NEC USA, Princeton, NJ

10A.2 Symmetry Detection and Dynamic Variable Ordering of Decision Diagrams
Shipra Panda, Fabio Somenzi, Univ. of Colorado, Boulder, CO, Bernard F. Plessier, Motorola, Inc., Austin. TX

10A.3 A Redesign Technique for Combinational Circuits Based on Reconnections of Gates
Yuji Kukimoto, Univ. of California, Berkeley, CA, Masahiro Fujita, Fujitsu Laboratories of America, San Jose, CA
Robert K. Brayton, Univ. of California, Berkeley, CA

SESSION 10B DESIGN FOR TEST AND CONCURRENT ERROR DETECTION

10B.1 Non-Scan Design-For-Testability of RT-Level Data Paths
Sujit Dey, Miodrag Potkonjak, C&C Research Labs., NEC USA, INC., Princeton, NJ

10B.2 Selecting Partial Scan Flip-Flops for Circuit Partitioning
Toshinobu Ono, NEC Corp., Kawasaki, Japan

10B.3 Logic Synthesis Techniques for Reduced Area Implementation of Multilevel Circuits with Concurrent Error Detection
Nur A. Touba, Edward J. McCluskey, Stanford Univ., Stanford, CA

SESSION 10C ANALOG MACROMODELING AND TEST

10C.1 Macromodeling of Analog Circuits for Hierarchical Circuit Design
Jianfeng Shao, Ramesh Harjani, Univ. of Minnesota, Minneapolis, MN

10C.2 Approximate Symbolic Analysis of Large Analog Integrated Circuits
Qicheng Yu, Carl Sechen, Univ. of Washington, Seattle, WA

10C.3 Testing of Analog Systems Using Behavioral Models and Optimal Experimental Design Techniques
Eric Felt, Alberto Sangiovanni-Vincentelli, Univ. of California, Berkeley, CA

SESSION 10D ROUTABILITY

10D.1 Layer Assignment for High-Performance Multi-Chip Modules
Kai-Yuan Chao, D.F. Wong, Univ. of Texas, Austin, TX

10D.2 The Reproducing Placement Problem with Applications
Wei-Liang Lin, Majid Sarrafzadeh, Northwestern Univ., Evanston, IL, C.K. Wong,

10D.3 RISA: Accurate and Efficient Placement Routability Modeling
Chih-liang Eric Cheng, Cadence Design Systems, Inc., San Jose, CA

SESSION 11A SEQUENTIAL OPTIMIZATION

11A.1 A New Approach for Factorizing FSM's
C. Rama Mohan, Cadence Design Systems Pvt. Ltd., Noida, India, P.P. Chakrabarti, Indian Inst. of Tech., Kharagpur, India

11A.2 Boolean Constrained Encoding: A New Formulation and a Case Study
N.L.V. Calazans, PUCRS, Porto Alegre, RS, Brazil

11A.3 Optimizing of Hierarchical Designs Using Partitioning and Resynthesis
Heinz-Josef Eikerling, Ralf Hunstock, Univ. of Raderborn, Paderborn, Germany

Raul Camposano, Synopsys, Inc., Mountain View, CA

SESSION 11B FAULT SIMULATION

11B.1 HyHOPE: A Fast Fault Simulator with Efficient Simulation of Hypertrophic Faults
Chen-Pin Kung, Chen-Shang Lin, National Taiwan Univ., Taiwan, ROC

11B.2 Fast Timing Simulation of Transient Faults in Digital Circuits
A. Dharchoudhury, Sung Mo Kang, Hungse Cha, Janak H. Patel, Univ. of Illinois, Urbana, IL

11B.3 A Fast and Memory-Efficient Diagnostic Fault Simulation for Sequential Circuits
Jer Min Jou, Shung-Chih Chen, National Cheng Kung Univ., Tainan, Taiwan, ROC

SESSION 11C TIMING ANALYSIS

11C.1 Timing Uncertainty Analysis for Time-of-Flight Systems
John R. Feehrer, Harry F. Jordan, Univ. of Colorado, Boulder, CO

11C.2 Provably Correct High-Level Timing Analysis Without Path Sensitization
S. Bhattacharya, Duke Univ., Durham, NC, Sujit Dey, C&C Research Labs., NEC USA, Inc., Princeton, NJ
Franc Brglez, North Carolina State Univ., Raleigh, NC

11C.3 A Timing Analysis Algorithm for Circuits with Level-Sensitive Latches
Jin-fuw Lee, Donald T. Tang, C.K. Wong, IBM Corp., Yorktown Heights, NY

SESSION 11D NEW CHALLENGES FOR DESIGN DATA MANAGEMENT: RE-USE AND HDL'S

11D.1 An Object-Oriented Cell Library Manager
Naresh K. Sehgal, Intel Corp., Santa Clara, CA, C.Y. Roger Chen, Syracuse Univ., Syracuse, NY, John M. Acken, Intel Corp., Santa Clara, CA

11D.2 Reuse of Design Objects in CAD Frameworks
Joachim Altmeyer, Stefan Ohnsorge, Bernd Schürmann, Univ. of Keiserslautern, Kaiserslautern, Germany

11D.3 Towards Support for Design Description Languages in EDA Frameworks
Olav Schetler, Susanne Heymann, GMD, Sankt Augustin, Germany

Author Index

Sessions