AUTHOR INDEX ASPDAC 97

[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [R] [S] [T] [V] [W] [X] [Y] [Z]

A

Agrawal, P.
RT Level Power Analysis
Akino, T.
A 2-Dimensional Transistor Placement for Cell Synthesis
Alzahrani, F.
A Real-Time High Performance Edge Detector for Computer Vision Applications
Amano, H.
An LSI Implementation of the Simple Serial Synchronized Multistage Interconnection Network
The DRT Network Router Chip
Anjo, K.-i.
The DRT Network Router Chip
Asada, K.
Crosstalk Noise in High Density and High Speed Interconnections due to Inductive Coupling
VLSI Design and Education Center (VDEC) Current Status and future plan

B

Banerjee, P.
A Procedure for Software Synthesis from VHDL Models
Barke, E.
Design Driven Partitioning
Becker, B.
On the Representational Power of Bit-Level and Word-Level Decision Diagrams
Learning Heuristics for OKFDD Minimization by Evolutionary Algorithms
Beerel, P.A.
RTL Verification of Timed Asynchronous and Heterogeneous Systems using Symbolic Model Checking
Behrens, D.
Design Driven Partitioning
Bhatia, D.
A Constructive Method for Data Path Area Estimation During High-Level VLSI Synthesis
Bian, J.
VIDE: A Visual VHDL Integrated Design Environment
Boku, T.
Advanced Processor Design using Hardware Description Language AIDL
Bombana, M.
Property Verification in the Design of Telecom Applications
Bouhabel, Y.
A New Approach for an AHDL Based on System Semantics
Bourai, Y.
A New Approach for an AHDL Based on System Semantics
Brouwers, J.
JavaTM in Electronic Design Automation

C

Cavalloro, P.
Property Verification in the Design of Telecom Applications
Cham, W.K.
Self-Timed 1-D ICT Processor
Chan, C.F.
Self-Timed 1-D ICT Processor
Chang, D.
Not Necessarily More Switches More Routability
Changge, Q.
VEAP: Global Optimization based Efficient Algorithm for VLSI Placement
Chen, D.-S.
Cube-Embedding Based State Encoding for Low Power Design
Chen, K.-C.
AQUILA: An Equivalence Verifier for Large Sequential Circuits
Chen, K. Y.
Structural Approach for Performance Driven ECC Circuit Synthesis
Chen, T.
A Real-Time High Performance Edge Detector for Computer Vision Applications
A CMOS Delayed Locked Loop (DLL) for Reducing Clock Skew to Under 500ps
Cheng, C.-K.
A New Layout-Driven Timing Model for Incremental Layout Optimization
A Building Block Placement Tool
BDD-based Logic Partitioning for Sequential Circuits
Cheng, K.-T.
AQUILA: An Equivalence Verifier for Large Sequential Circuits
Cheung, T. K.-Y.
A Transformational Codesign Methodology
Chiodo, M.
Trade-off Evaluation in Embedded System Design Via Co-simulation
Cho, C.-H.
A Quantitative Analysis for Optimizing Memory Allocation
Cho, D.H.
Interconnect Capacitances, Crosstalk, and Signal Delay in High Speed and High Density VLSI Circuits (No Paper Submitted)
Choi, H.
Verification Methodology of Compatible Microprocessors
HK386: An x86-Compatible 32bit CICS Microprocessor
Choi, S.
Optimal Loop Bandwidth Design for Low Noise PLL Applications
Choi, W.-C.
Simulation of Gate Switching Characteristics on a Miniaturized MOSFET based on a Non-Isothermal Non-Equilibrium Transport Model
Chou, T.-L.
Statistical Estimation of Combinational and Sequential CMOS Digital Circuit Activity Considering Uncertainty of Gate Delay
Choy, O.C.S.
Self-Timed 1-D ICT Processor
Cong, J.
Modeling and Layout Optimization of VLSI Devices and Interconnects in Deep Submicron Design

D

Dai, W. W.-M.
General Floorplanning with L-shaped, T-shaped and Soft Blocks Based on Bounded Slicing Grid Structure
Bit-Serial Pipeline Synthesis and Layout for Large-Scale Configurable Systems
Dang, R.
Simulation of Gate Switching Characteristics on a Miniaturized MOSFET based on a Non-Isothermal Non-Equilibrium Transport Model
Das, C.
The EUROPRACTICE MPC Service
Debnath, D.
An Optimization of AND-OR-EXOR Three-level Networks
Denyer, P.
JavaTM in Electronic Design Automation
Ding, C.
Statistical Design of Macro-models For RT-level Power Evaluation
Dömer, R.
Built-in Chaining: Introducing Complex Components into Architectural Synthesis
Drechsler, R.
On the Representational Power of Bit-Level and Word-Level Decision Diagrams
Learning Heuristics for OKFDD Minimization by Evolutionary Algorithms
Dufour, J.
A Building Block Placement Tool

E

Enders, R.
On the Representational Power of Bit-Level and Word-Level Decision Diagrams
Endo, M.
Polling-based Real-time Software for MPEG2 System Protocol LSIs
Etoh, H.
Topological Routing Path Search Algorithm with Incremental Routability Test

F

Fang, W.-J.
DP-Gen: A Datapath Generator for Multiple-FPGA Applications
Feldmann, P.
A New Linear-Time Harmonic Balance Algorithm for Cyclostationary Noise Analysis in RF Circuits
Ferrandi, F.
Property Verification in the Design of Telecom Applications
Fujioka, H.
Hierarchical Fault Tracing for VLSI Sequential Circuits from CAD Layout Data in the CAD-linked EB Test System
Fujita, M.
Delay Estimation on Optimization of Logic Circuits: A Survey
BDD-based Logic Partitioning for Sequential Circuits
Fujiwara, H.
Non-Scan Design for Testable Data Paths Using Thru Operation
Fujiyoshi, K.
A Mapping from Sequence-Pair to Rectangular Dissection
Fukami, K.
A Co-evaluation of FPGA Architectures and the CAD System for Telecommunication
Fukui, M.
A 2-Dimensional Transistor Placement for Cell Synthesis
Fummi, F.
The Use of Hierarchical Information to Test Large Controllers

G

Gajski, D. D.
RT Level Power Analysis
A Quantitative Analysis for Optimizing Memory Allocation
RT Level Power Analysis
Ganz, A.
Reducing the Complexity of Path Classification by Reconvergence Analysis
Gerber, S.
AND/OR Reasoning Graphs for Determining Prime Implicants in Multi-Level Combinational Networks
Göckel, N.
Learning Heuristics for OKFDD Minimization by Evolutionary Algorithms
Guo, H.
Power Consumption in CMOS Combinational Logic Blocks at High Frequencies
Gupta, A.
A Constructive Method for Data Path Area Estimation During High-Level VLSI Synthesis
Gupta, R. K.
Hardware-Software Co-design: Tools for Architecting Systems-On-A-Chip
A Procedure for Software Synthesis from VHDL Models

H

Hachiya, K.
Enhancement of Parallelism for Tearing-based Circuit Simulation
Hama, T.
Topological Routing Path Search Algorithm with Incremental Routability Test
Hanyu, T.
Low-Power Multiple-Valued Current-Mode Integrated Circuit with Current-Source Control and Its Application
Hayashi, T.
An Enhanced Iterative Improvement Method for Evaluating the Maximum Number of Simultaneous Switching Gates for Combinational Circuits
Hayashi, T.
A Co-evaluation of FPGA Architectures and the CAD System for Telecommunication
Hellestrand, G.
A Transformational Codesign Methodology
Henftling, M.
Reducing the Complexity of Path Classification by Reconvergence Analysis
Hillawi, J.
Choosing a Digital Simulator
Hiramine, M.
A Rapid Prototyping Method for Top-Down Design of System-on-Chip Devices Using LPGAs
Hirata, T.
Efficient Routability Checking for Global Wires in Planar Layouts
Hirose, F.
Acceleration of Mincut Partitioning using Hardware CAD Accelerator TP5000
Hoh, K.
VLSI Design and Education Center (VDEC) Current Status and future plan
Hong, H.-C.
Analysis and Design of Multiple-Bit High-Order E-^ Modulator
Hong, S.K.
HK386: An x86-Compatible 32bit CICS Microprocessor
Hong, Y.-S.
A Quantitative Analysis for Optimizing Memory Allocation
Hsieh, C.
Statistical Design of Macro-models For RT-level Power Evaluation
Hsu, Y.-C.
On the Share-routine Implementation of Subprogram Synthesis
Huang, I.-J.
Synthesis and Analysis of an Industrial Embedded Microcontroller
Huang, J.-D.
BDD Based Lambda Set Selection in Roth-Karp Decomposition for LUT Architecture
Huang, S.-Y.
AQUILA: An Equivalence Verifier for Large Sequential Circuits
Hwang, C.-H.
An Entropy Measure for Power Estimation of Boolean Functions
Hwang, C.-T.
Evaluating Cost-Performance Tradeoffs for System Level Applications
On the Share-routine Implementation of Subprogram Synthesis
Hwang, J.-S.
Multi-Project Chip Service for University and Industry in Taiwan

I

Iguchi, Y.
On Properties of Kleene TDDs
Iida, T.
A Current-mode,3V,20MHz, 9-bit equivalent CMOS Sample-and-Hold Circuit
Imai, M.
VLSI Implementation of a Real-time Operating System
Ing, W.-L.
Evaluating Cost-Performance Tradeoffs for System Level Applications
Inoue, M.
Non-Scan Design for Testable Data Paths Using Thru Operation
Iso, N.
Efficient Routability Checking for Global Wires in Planar Layouts
Isshiki, T.
Bit-Serial Pipeline Synthesis and Layout for Large-Scale Configurable Systems
Ito, K.
High Speed Bit-Serial Parallel Processing on Array Architecture
An Optimal Scheduling Method for Parallel Processing System of Array Architecture
Ito, Y.
A Hardware/Software Co-simulation Environment for Micro-processor Design with HDL Simulator and OS interface
Iwasaki, C.
A RTL Partitioning Method with a Fast Min-Cut Improvement Algorithm
Iwata, T.
An Optimal Scheduling Method for Parallel Processing System of Array Architecture
Izawa, T.
Microelectronics Evolution Brings Real Multimedia Era
Izeboudjen, N.
A New Approach for an AHDL Based on System Semantics

J

Jemai, A.
Embedded Architectural Simulation within Behavioral Synthesis Environment
Jerraya, A.A.
Embedded Architectural Simulation within Behavioral Synthesis Environment
Jiang, J.-H.
BDD Based Lambda Set Selection in Roth-Karp Decomposition for LUT Architecture
John, W.
EMC-Adequate Design of Printed Circuit Board as a Part of the System Development
Jou, J.-Y.
A Power Driven Two-Level Logic Optimizer
BDD Based Lambda Set Selection in Roth-Karp Decomposition for LUT Architecture
Jou, S.-J.
Structural Approach for Performance Driven ECC Circuit Synthesis

K

Kajitani, Y.
Performance and Reliability Driven Clock Scheduling of Sequential Logic Circuits
A Mapping from Sequence-Pair to Rectangular Dissection
Kambe, T.
A Testability Analysis Method for Register-Transfer Level Descriptions
Architecture Evaluation Based on the Datapath Structure and Parallel Constraint
Kamei, T.
An LSI Implementation of the Simple Serial Synchronized Multistage Interconnection Network
Kameyama, M.
Low-Power Multiple-Valued Current-Mode Integrated Circuit with Current-Source Control and Its Application
Kaneko, M.
Concurrent Cell Generation and Mapping for CMOS Logic Circuits
Kang, M.
General Floorplanning with L-shaped, T-shaped and Soft Blocks Based on Bounded Slicing Grid Structure
Kang, Y.J.
HK386: An x86-Compatible 32bit CICS Microprocessor
Kanthamanon, P.
A Transformational Codesign Methodology
Katkoori, S.
A Constructive Method for Data Path Area Estimation During High-Level VLSI Synthesis
Kawaguchi, K.
A RTL Partitioning Method with a Fast Min-Cut Improvement Algorithm
Kawaguchi, Y.
Efficient Routability Checking for Global Wires in Planar Layouts
Kawahima, H.
Simulation of Gate Switching Characteristics on a Miniaturized MOSFET based on a Non-Isothermal Non-Equilibrium Transport Model
Kazama, S.
Low-Power Multiple-Valued Current-Mode Integrated Circuit with Current-Source Control and Its Application
Kim, B.
Optimal Loop Bandwidth Design for Low Noise PLL Applications
Kim, D.T.
HK386: An x86-Compatible 32bit CICS Microprocessor
Kim, J.S.
HK386: An x86-Compatible 32bit CICS Microprocessor
Kim, N.H.
Interconnect Capacitances, Crosstalk, and Signal Delay in High Speed and High Density VLSI Circuits (No Paper Submitted)
Kim, T.-H.
Verification Methodology of Compatible Microprocessors
Single Cycle Access Cache for the Misaligned Data and Instruction Prefetch
Kim, Y.-B.
A CMOS Delayed Locked Loop (DLL) for Reducing Clock Skew to Under 500ps
Kinoshita, M.
A Functional Memory Type Parallel Processor for Vector Quantization
Kirihara, M.
Monte Carlo Simulation for Single Electron Circuits
Kission, P.
Embedded Architectural Simulation within Behavioral Synthesis Environment
Kita, H.
An Enhanced Iterative Improvement Method for Evaluating the Maximum Number of Simultaneous Switching Gates for Combinational Circuits
Kobayashi, K.
A Functional Memory Type Parallel Processor for Vector Quantization
Koide, T.
Par-POPINS: A Timing-Driven Parallel Placement Method with the Elmore Delay Model for Row Based VLSIs
Koizumi, H.
A Rapid Prototyping Method for Top-Down Design of System-on-Chip Devices Using LPGAs
Komatsudaira, Y.
VLSI Implementation of a Real-time Operating System
Kondo, M.
A Current Mode Cyclic A/D Converter with a 0.8um CMOS Process
Kong, B.S.
HK386: An x86-Compatible 32bit CICS Microprocessor
Konishi, K.
Super Low Power 8-bit CPU with Pass-Transistor Logic
Krishnaswamy, V.
A Procedure for Software Synthesis from VHDL Models
Kudoh, T.
The DRT Network Router Chip
Kunieda, H.
High Speed Bit-Serial Parallel Processing on Array Architecture
Bit-Serial Pipeline Synthesis and Layout for Large-Scale Configurable Systems
An Optimal Scheduling Method for Parallel Processing System of Array Architecture
Kunz, W.
AND/OR Reasoning Graphs for Determining Prime Implicants in Multi-Level Combinational Networks
Kuo, C.-W.
On Synthesis of Speed-Independent Circuits at STG Level
Kuo, M.-T.
BDD-based Logic Partitioning for Sequential Circuits
Kurdahi, F.
ChipEst-FPGA: A Tool for Chip Level Area and Timing Estimation of Lookup Table Based FPGAs for High Level Applications
Kyung, C.-M.
CBLO: A Clustering Based Linear Ordering Algorithm for Netlist Partitioning
Verification Methodology of Compatible Microprocessors
HK386: An x86-Compatible 32bit CICS Microprocessor
Single Cycle Access Cache for the Misaligned Data and Instruction Prefetch
Multi-Project Chip Activities in Korea-IDEC Perspective-

L

Landwehr, B.
Built-in Chaining: Introducing Complex Components into Architectural Synthesis
Lavagno, L.
Trade-off Evaluation in Embedded System Design Via Co-simulation
Lee, B.-Y.
Super Low Power 8-bit CPU with Pass-Transistor Logic
Lee, G.
Logic Synthesis for Cellular Architecture FPGAs Using BDDs
Lee, H.-C.
Verification Methodology of Compatible Microprocessors
Single Cycle Access Cache for the Misaligned Data and Instruction Prefetch
Lee, M. T.-C.
On the Share-routine Implementation of Subprogram Synthesis
Lee, S.-J.
Verification Methodology of Compatible Microprocessors
Lee, S.J.
HK386: An x86-Compatible 32bit CICS Microprocessor
Lee, Y.-H.
Verification Methodology of Compatible Microprocessors
Lee, Y.S.
Fault Coverage Improvement Based on Error Signal Analysis
Li, S. C.
+-1.5V CMOS Four-Quardrant Multiplier
Lillis, J.
A New Layout-Driven Timing Model for Incremental Layout Optimization
Lim, K.
Optimal Loop Bandwidth Design for Low Noise PLL Applications
Lin, B.-H.
Analysis and Design of Multiple-Bit High-Order E-^ Modulator
Lin, J.-Y.
CB-Power: A Hierarchical Cell-Based Power Characterization and Estimation Environment for Static CMOS Circuits
Lin, K.-J.
On Synthesis of Speed-Independent Circuits at STG Level
Lin, T.-C.
DP-Gen: A Datapath Generator for Multiple-FPGA Applications
Lin, Y.-L.
Computing Brokerage and Its Applications in VLSI Design
An Improved Objective for Cell Placement
Liu, F.-J.
A New Layout-Driven Timing Model for Incremental Layout Optimization
Lu, J.-M.
CB-Power: A Hierarchical Cell-Based Power Characterization and Estimation Environment for Static CMOS Circuits

M

Maeng, S.R.
HK386: An x86-Compatible 32bit CICS Microprocessor
Marculescu, D.
Adaptive Models for Input Data Compaction for Power Simulators
Marculescu, R.
Adaptive Models for Input Data Compaction for Power Simulators
Marek-Sadowska, M.
Not Necessarily More Switches More Routability
Marwedel, P.
Design and Test of Processor-Core Based Systems
Built-in Chaining: Introducing Complex Components into Architectural Synthesis
Masuzawa, T.
Non-Scan Design for Testable Data Paths Using Thru Operation
Matsuura, A.
An Efficient Hierarchical Clustering Method for the Multiple Constant Multiplication Problem
Matsuura, M.
On Properties of Kleene TDDs
McBride, R.
A Building Block Placement Tool
Mido, T.
Crosstalk Noise in High Density and High Speed Interconnections due to Inductive Coupling
Min, Y.
Fault Coverage Improvement Based on Error Signal Analysis
Miura, K.
Hierarchical Fault Tracing for VLSI Sequential Circuits from CAD Layout Data in the CAD-linked EB Test System
Morikawa, S.
A High Performance FIR Filter Dedicated to Digital Video Transmission
Morimoto, T.
Advanced Processor Design using Hardware Description Language AIDL
Muraoka, M.
A RTL Partitioning Method with a Fast Min-Cut Improvement Algorithm
Murata, H.
A Mapping from Sequence-Pair to Rectangular Dissection
Murgai, R.
Delay Estimation on Optimization of Logic Circuits: A Survey

N

Naganuma, J.
Polling-based Real-time Software for MPEG2 System Protocol LSIs
Nagoya, A.
An Efficient Hierarchical Clustering Method for the Multiple Constant Multiplication Problem
Nakamae, K.
Hierarchical Fault Tracing for VLSI Sequential Circuits from CAD Layout Data in the CAD-linked EB Test System
Nakamura, H.
Advanced Processor Design using Hardware Description Language AIDL
Nakamura, Y.
A Hardware/Software Co-simulation Environment for Micro-processor Design with HDL Simulator and OS interface
Nakano, T.
VLSI Implementation of a Real-time Operating System
Nakaoka, T.
Architecture Evaluation Based on the Datapath Structure and Parallel Constraint
Nakata, T.
Enhancement of Parallelism for Tearing-based Circuit Simulation
Nakazawa, K.
Advanced Processor Design using Hardware Description Language AIDL
Natesan, V.
A Constructive Method for Data Path Area Estimation During High-Level VLSI Synthesis
Nishi, H.
The DRT Network Router Chip
Nishimaru, Y.
Par-POPINS: A Timing-Driven Parallel Placement Method with the Elmore Delay Model for Row Based VLSIs
Nishimura, K.
The DRT Network Router Chip
Noda, H.
A Testability Analysis Method for Register-Transfer Level Descriptions

O

Ochi, H.
ASAver.1: An FPGA-Based Education Board for Computer Architecture/System Design
Oh, H.-S.
Verification Methodology of Compatible Microprocessors
Ohtsuki, T.
A Simultaneous Placement and Global Routing Algorithm with Path Length Constraints for Transport-Processing FPGAs
Okada, K.
A High Performance FIR Filter Dedicated to Digital Video Transmission
Okino, K.
A Rapid Prototyping Method for Top-Down Design of System-on-Chip Devices Using LPGAs
Okumura, M.
A Time-Domain Method for Numerical Noise Analysis of Oscillators
Ono, M.
Par-POPINS: A Timing-Driven Parallel Placement Method with the Elmore Delay Model for Row Based VLSIs
Onodera, H.
A Functional Memory Type Parallel Processor for Vector Quantization
A Current Mode Cyclic A/D Converter with a 0.8um CMOS Process
Or-Bach, Z.
A Rapid Prototyping Method for Top-Down Design of System-on-Chip Devices Using LPGAs

P

Pang, J.T.C.
Self-Timed 1-D ICT Processor
Parameswaran, S.
Power Consumption in CMOS Combinational Logic Blocks at High Frequencies
Park, B.-I.,
Single Cycle Access Cache for the Misaligned Data and Instruction Prefetch
Park, C.-J.
Verification Methodology of Compatible Microprocessors
Single Cycle Access Cache for the Misaligned Data and Instruction Prefetch
Park, H.S.
Interconnect Capacitances, Crosstalk, and Signal Delay in High Speed and High Density VLSI Circuits (No Paper Submitted)
Park, I.-C.
Verification Methodology of Compatible Microprocessors
HK386: An x86-Compatible 32bit CICS Microprocessor
Single Cycle Access Cache for the Misaligned Data and Instruction Prefetch
Multi-Project Chip Activities in Korea-IDEC Perspective-
Park, J.-H.
Performance Test of Viterbi Decoder for Wideband CDMA System
Park, S.H.
HK386: An x86-Compatible 32bit CICS Microprocessor
Passerone, C.
Trade-off Evaluation in Embedded System Design Via Co-simulation
Pedram, M.
A Note on the Relationship Between Signal Probability and Switching Activity
Adaptive Models for Input Data Compaction for Power Simulators
Statistical Design of Macro-models For RT-level Power Evaluation
A New Description of CMOS Circuits at Switch-Level

R

Rao, L.
Parallel Calculation of 3-D Parasitic Resistance and Capacitance with Linear Boundary Elements
Rho, Y.-C.
Performance Test of Viterbi Decoder for Wideband CDMA System
Roy, K.
Statistical Estimation of Combinational and Sequential CMOS Digital Circuit Activity Considering Uncertainty of Gate Delay
Efficient Synthesis of AND/XOR Networks
Roychowdhury, J.S.
A New Linear-Time Harmonic Balance Algorithm for Cyclostationary Noise Analysis in RF Circuits

S

Saika, S.
A 2-Dimensional Transistor Placement for Cell Synthesis
Saito, K.
Advanced Processor Design using Hardware Description Language AIDL
Saito, T.
Enhancement of Parallelism for Tearing-based Circuit Simulation
Sakurai, R.
A Testability Analysis Method for Register-Transfer Level Descriptions
Sangiovanni-Vincentelli, A.
Trade-off Evaluation in Embedded System Design Via Co-simulation
Sano, M.
Acceleration of Mincut Partitioning using Hardware CAD Accelerator TP5000
Sansoe, C.
Trade-off Evaluation in Embedded System Design Via Co-simulation
Sarrafzadeh, M.
Cube-Embedding Based State Encoding for Low Power Design
Sasahara, M.
An LSI Implementation of the Simple Serial Synchronized Multistage Interconnection Network
Sasao, T.
On Properties of Kleene TDDs
An Optimization of AND-OR-EXOR Three-level Networks
Sato, M.
A Simultaneous Placement and Global Routing Algorithm with Path Length Constraints for Transport-Processing FPGAs
Schrage, J.
Modelling and Detection of Dynamic Errors due to Reflection - and Crosstalk-Noise
Sciuto, D.
The Use of Hierarchical Information to Test Large Controllers
Seo, K.
A Rapid Prototyping Method for Top-Down Design of System-on-Chip Devices Using LPGAs
Seong, K.S.
CBLO: A Clustering Based Linear Ordering Algorithm for Netlist Partitioning
HK386: An x86-Compatible 32bit CICS Microprocessor
Seung, M.H.
Interconnect Capacitances, Crosstalk, and Signal Delay in High Speed and High Density VLSI Circuits (No Paper Submitted)
Shen, W.-Z.
CB-Power: A Hierarchical Cell-Based Power Characterization and Estimation Environment for Static CMOS Circuits
Shi, C.-J. R.
Block-Level Fault Isolation Using Partition Theory and Logic Minimization Techniques
Solving Constrained Via Minimization by Compact Linear Programming
Shimizugashira, T.
High Speed Bit-Serial Parallel Processing on Array Architecture
Shimogori, S.
Acceleration of Mincut Partitioning using Hardware CAD Accelerator TP5000
Shinomiya, N.
A 2-Dimensional Transistor Placement for Cell Synthesis
Shiomi, A.
VLSI Implementation of a Real-time Operating System
Shirakawa, I.
A High Performance FIR Filter Dedicated to Digital Video Transmission
Song, H.-J.
Multi-Project Chip Activities in Korea-IDEC Perspective-
Stoffel, D.
AND/OR Reasoning Graphs for Determining Prime Implicants in Multi-Level Combinational Networks
Su, C.
Structural Approach for Performance Driven ECC Circuit Synthesis
Su, H.-P.
An Improved Objective for Cell Placement
Su, M.
VIDE: A Visual VHDL Integrated Design Environment
Suen, A.-N.
A Programmable Application-Specific VLSI Architecture and Implementation for Speech Word-Recognizer
Sugimoto, Y.
A Current-mode,3V,20MHz, 9-bit equivalent CMOS Sample-and-Hold Circuit
Suzuki, F.
A Rapid Prototyping Method for Top-Down Design of System-on-Chip Devices Using LPGAs

T

Tafat, A.
A New Approach for an AHDL Based on System Semantics
Tafertshofer, P.
Reducing the Complexity of Path Classification by Reconvergence Analysis
Takabatake, K.
Non-Scan Design for Testable Data Paths Using Thru Operation
Takahara, A.
A Co-evaluation of FPGA Architectures and the CAD System for Telecommunication
Takahashi, A.
Performance and Reliability Driven Clock Scheduling of Sequential Logic Circuits
Takahashi, M.
A Testability Analysis Method for Register-Transfer Level Descriptions
Takase, H.
An Enhanced Iterative Improvement Method for Evaluating the Maximum Number of Simultaneous Switching Gates for Combinational Circuits
Takeuchi, M.
A Functional Memory Type Parallel Processor for Vector Quantization
Takeuchi, S.
A High Performance FIR Filter Dedicated to Digital Video Transmission
Taki, K.
Super Low Power 8-bit CPU with Pass-Transistor Logic
Tamaru, K.
A Functional Memory Type Parallel Processor for Vector Quantization
A Current Mode Cyclic A/D Converter with a 0.8um CMOS Process
Tamiya, Y.
Delay Estimation for Technology Independent Synthesis
Tanabe, N.
Enhancement of Parallelism for Tearing-based Circuit Simulation
Tanaka, H.
Super Low Power 8-bit CPU with Pass-Transistor Logic
Taniguchi, K.
Monte Carlo Simulation for Single Electron Circuits
Tanimoto, H.
A Time-Domain Method for Numerical Noise Analysis of Oscillators
Tian, J.
Concurrent Cell Generation and Mapping for CMOS Logic Circuits
Tianming, K.
VEAP: Global Optimization based Efficient Algorithm for VLSI Placement
Togawa, N.
A Simultaneous Placement and Global Routing Algorithm with Path Length Constraints for Transport-Processing FPGAs
Tolkiehn, R.
Design Driven Partitioning
Tsay, Y.-W.
An Improved Objective for Cell Placement
Tseng, J.-M.
A Power Driven Two-Level Logic Optimizer
Tseng, W.-D.
Fuzzy-based Circuit Partitioning in Built-in Current Testing
Tsukiyama, S.
Not Necessarily More Switches More Routability

V

Vachoux, A.
VHDL Analog and Mixed-Signal Extensions Through Examples
Vakilotojar, V.
RTL Verification of Timed Asynchronous and Heterogeneous Systems using Symbolic Model Checking
Vemuri, R.
A Constructive Method for Data Path Area Estimation During High-Level VLSI Synthesis

W

Wakabayashi, S.
Par-POPINS: A Timing-Driven Parallel Placement Method with the Elmore Delay Model for Row Based VLSIs
Wang, J.-F.
A Programmable Application-Specific VLSI Architecture and Implementation for Speech Word-Recognizer
Wang, K.
Fuzzy-based Circuit Partitioning in Built-in Current Testing
Wang, L.-R.
Synthesis and Analysis of an Industrial Embedded Microcontroller
Wang, T.-D.
A Programmable Application-Specific VLSI Architecture and Implementation for Speech Word-Recognizer
Wang, Y.
BDD-based Logic Partitioning for Sequential Circuits
Wang, Y.-M.
Synthesis and Analysis of an Industrial Embedded Microcontroller
Wang, Z.
Parallel Calculation of 3-D Parasitic Resistance and Capacitance with Linear Boundary Elements
Watanabe, T.
A Mapping from Sequence-Pair to Rectangular Dissection
Watanabe, T.
Multi-Pride: A System for Supporting Multi-Layered Printed Wiring Board Design
Wei, J.-S.
BDD Based Lambda Set Selection in Roth-Karp Decomposition for LUT Architecture
Weng, H.-C.
On the Share-routine Implementation of Subprogram Synthesis
Weste, N.
Some Thoughts on Process Retargettable and Reusable IC Intellectual Property
Won, N.
Verification Methodology of Compatible Microprocessors
Wong, M.W.T.
Fault Coverage Improvement Based on Error Signal Analysis
Wu, A. C.-H.
An Entropy Measure for Power Estimation of Boolean Functions
Evaluating Cost-Performance Tradeoffs for System Level Applications
DP-Gen: A Datapath Generator for Multiple-FPGA Applications
Wu, C.-W.
Analysis and Design of Multiple-Bit High-Order E-^ Modulator
Wu, Q.
A Note on the Relationship Between Signal Probability and Switching Activity
Statistical Design of Macro-models For RT-level Power Evaluation
Wu, X.
A Note on the Relationship Between Signal Probability and Switching Activity
A New Description of CMOS Circuits at Switch-Level
Wu, Y.-L.
Not Necessarily More Switches More Routability

X

Xianlong, H.
VEAP: Global Optimization based Efficient Algorithm for VLSI Placement
Xu, M.
ChipEst-FPGA: A Tool for Chip Level Area and Timing Estimation of Lookup Table Based FPGAs for High Level Applications
Xue, H.
VIDE: A Visual VHDL Integrated Design Environment

Y

Yamada, A.
Architecture Evaluation Based on the Datapath Structure and Parallel Constraint
Yamaguchi, M.
Architecture Evaluation Based on the Datapath Structure and Parallel Constraint
Yang, W.-S.
Verification Methodology of Compatible Microprocessors
Yasuura, H.
A Rapid Prototyping Method for Top-Down Design of System-on-Chip Devices Using LPGAs
Ye, Y.
Efficient Synthesis of AND/XOR Networks
Yen, T.-Y.
DP-Gen: A Datapath Generator for Multiple-FPGA Applications
Yim, J.-S.
Verification Methodology of Compatible Microprocessors
Single Cycle Access Cache for the Misaligned Data and Instruction Prefetch
Yukishita, M.
An Efficient Hierarchical Clustering Method for the Multiple Constant Multiplication Problem

Z

Zhang, K.
An Enhanced Iterative Improvement Method for Evaluating the Maximum Number of Simultaneous Switching Gates for Combinational Circuits
Zhang, P.
A Building Block Placement Tool
Zhou, W.
Parallel Calculation of 3-D Parasitic Resistance and Capacitance with Linear Boundary Elements
Zhou, Y.
Fault Coverage Improvement Based on Error Signal Analysis
Zhu, J.
RT Level Power Analysis