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ASPDAC 97 :
[ <A HREF="aspabs.htm">Abstracts</A> ]
[ <A HREF="aspsess.htm">Session Index</A> ]
[ <A HREF="aspai.htm">Author Index</A> ]</H3>
<HR>
<H2>TABLE OF CONTENTS ASPDAC 97</H2>
<B>
Sessions:
[<A HREF="#keynote1">Keynote I</A>]
[<A HREF="#sess1a">1A</A>]
[<A HREF="#sess1b">1B</A>]
[<A HREF="#sess1c">1C</A>]
[<A HREF="#sess1d">1D</A>]
[<A HREF="#sess2a">2A</A>]
[<A HREF="#sess2b">2B</A>]
[<A HREF="#sess2c">2C</A>]
[<A HREF="#sess2d">2D</A>]
[<A HREF="#sess3a">3A</A>]
[<A HREF="#sess3b">3B</A>]
[<A HREF="#sess3c">3C</A>]
[<A HREF="#sess3d">3D</A>]
[<A HREF="#keynote2">Keynote II</A>]
[<A HREF="#sess4a">4A</A>]
[<A HREF="#sess4b">4B</A>]
[<A HREF="#sess4c">4C</A>]
[<A HREF="#sess4d">4D</A>]
[<A HREF="#sess5a">5A</A>]
[<A HREF="#sess5b">5B</A>]
[<A HREF="#sess5c">5C</A>]
[<A HREF="#sess5d">5D</A>]
[<A HREF="#sess6a">6A</A>]
[<A HREF="#sess6b">6B</A>]
[<A HREF="#sess6c">6C</A>]
[<A HREF="#sess6d">6D</A>]
[<A HREF="#keynote3">Keynote III</A>]
[<A HREF="#sess7a">7A</A>]
[<A HREF="#sess7b">7B</A>]
[<A HREF="#sess7c">7C</A>]
[<A HREF="#sess7d">7D</A>]
[<A HREF="#sess8a">8A</A>]
[<A HREF="#sess8b">8B</A>]
[<A HREF="#sess8c">8C</A>]
[<A HREF="#sess8d">8D</A>]
[<A HREF="#sess9a">9A</A>]
[<A HREF="#sess9b">9B</A>]
[<A HREF="#sess9c">9C</A>]
[<A HREF="#sess9d">9D</A>]<P>
<A HREF="order.htm">Title and Copyright</A><BR>
<A HREF="aspfm.htm#orgcom">Organizing Committee</A><BR>
<A HREF="aspfm.htm#techcom">Technical Program Committee</A><BR>
<A HREF="aspfm.htm#advisory">Advisory Board</A><BR>
<A HREF="aspfm.htm#steercom">Steering Committee</A><BR>
<A HREF="aspfm.htm#genchair">General Chair's Message</A><BR>
<A HREF="aspfm.htm#chair">Program Chair's Message</A><BR>
<A HREF="aspfm.htm#contest">ASP-DAC '97 University LSI Design Contest</A><BR>
<A HREF="aspfm.htm#cfp">Call for Papers</A><BR>
<A HREF="aspfm.htm#bestpapr">Best Paper Awards</A><P>
<HR>
<DL>
<H2><A NAME="keynote1"> Keynote Address I:</A></H2>
<A HREF="aspabs.htm#keynote1"><IMG SRC="../../../../absicon.gif"></A>
Microelectronics Evolution Brings Real Multimedia Era</A>
<DD><I>Tatsuo Izawa, NTT Science and Core Technology Laboratory Group, Japan</I>
</DL>
<HR>
<H2>Session 1A : <A HREF="aspabs.htm#sess1a" NAME="sess1a">
Rapid Prototyping
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#01a_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
1A.1 A Co-evaluation of FPGA Architectures and the CAD System for
Telecommunication</A>
<DD><I> Tsunemasa Hayashi, Atsushi Takahara, Ken-nosuke Fukami</I><P>
<DT>
<A HREF="aspabs.htm#01a_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
1A.2 A Rapid Prototyping Method for Top-Down Design of System-on-Chip
Devices Using LPGAs</A>
<DD><I>Fumio Suzuki, Katsuhiko Seo, Hisao Koizumi, Masanobu Hiramine, Hiroto
Yasuura, Kazuo Okino, Zvi Or-Bach</I><P>
<DT>
<A HREF="aspabs.htm#01a_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
1A.3 Performance Test of Viterbi Decoder for Wideband CDMA System</A>
<DD><I>Jang-Hyun Park, Yeo-Chul Rho</I><P>
</DL>
<HR>
<H2>Session 1B : <A HREF="aspabs.htm#sess1b" NAME="sess1b">
Delay Estimation and Optimization
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#01b_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
1B.1 Delay Estimation on Optimization of Logic Circuits: A Survey</A>
<DD><I>Masahiro Fujita, Rajeev Murgai</I><P>
<DT>
<A HREF="aspabs.htm#01b_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
1B.2 Delay Estimation for Technology Independent Synthesis</A>
<DD><I>Yutaka Tamiya</I><P>
<DT>
<A HREF="aspabs.htm#01b_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
1B.3 Performance and Reliability Driven Clock Scheduling of Sequential Logic
Circuits</A>
<DD><I>Atsushi Takahashi, Yoji Kajitani</I><P>
</DL>
<HR>
<H2>Session 1C : <A HREF="aspabs.htm#sess1c" NAME="sess1c">
Circuit Partitioning
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#01c_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
1C.1 CBLO: A Clustering Based Linear Ordering Algorithm for Netlist
Partitioning</A>
<DD><I>K.S. Seong, C.-M. Kyung</I><P>
<DT>
<A HREF="aspabs.htm#01c_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
1C.2 Design Driven Partitioning</A>
<DD><I>Dirk Behrens, Robert Tolkiehn, Erich Barke</I><P>
<DT>
<A HREF="aspabs.htm#01c_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
1C.3S A RTL Partitioning Method with a Fast Min-Cut Improvement Algorithm</A>
<DD><I>Kenichi Kawaguchi, Chie Iwasaki, Michiaki Muraoka</I><P>
<DT>
<A HREF="aspabs.htm#01c_4"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
1C.4S Acceleration of Mincut Partitioning using Hardware CAD Accelerator
TP5000</A>
<DD><I>Masahiro Sano, Shintaro Shimogori, Fumiyasu Hirose</I><P>
</DL>
<HR>
<DL>
<H2><A NAME="sess1d">Session 1D : Invited Talk</A></H2>
<A HREF="aspabs.htm#sess1d"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
Computing Brokerage and Its Applications in VLSI Design</A>
<DD><I>Youn-Long Lin</I><P>
</DL>
<HR>
<H2>Session 2A : <A HREF="aspabs.htm#sess2a" NAME="sess2a">
Application Specific Design
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#02a_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
2A.1 A Programmable Application-Specific VLSI Architecture and Implementation
for Speech Word-Recognizer</A>
<DD><I>An-Nan Suen, Jhing-Fa Wang, Tswen-Duh Wang</I><P>
<DT>
<A HREF="aspabs.htm#02a_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
2A.2 A High Performance FIR Filter Dedicated to Digital Video Transmission</A>
<DD><I>Shun Morikawa, Keisuke Okada, Isao Shirakawa, Sumitaka Takeuchi</I><P>
<DT>
<A HREF="aspabs.htm#02a_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
2A.3 An Efficient Hierarchical Clustering Method for the Multiple Constant
Multiplication Problem</A>
<DD><I>Akihiro Matsuura, Mitsuteru Yukishita, Akira Nagoya</I><P>
<DT>
<A HREF="aspabs.htm#02a_4"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
2A.4 Structural Approach for Performance Driven ECC Circuit Synthesis</A>
<DD><I>Chau-Chin Su, Kathy Y. Chen, Shyh-Jye Jou</I><P>
</DL>
<HR>
<H2>Session 2B : <A HREF="aspabs.htm#sess2b" NAME="sess2b">
Power: Estimation and Synthesis
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#02b_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
2B.1 Statistical Estimation of Combinational and Sequential
CMOS Digital Circuit Activity Considering Uncertainty of Gate Delay</A>
<DD><I>Tan-Li Chou, Kaushik Roy</I><P>
<DT>
<A HREF="aspabs.htm#02b_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
2B.2 An Entropy Measure for Power Estimation of Boolean Functions</A>
<DD><I>Chi-Hong Hwang, Allen Chung-Hao Wu</I><P>
<DT>
<A HREF="aspabs.htm#02b_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
2B.3 An Enhanced Iterative Improvement Method for Evaluating the Maximum
Number of Simultaneous Switching Gates for Combinational Circuits</A>
<DD><I>Kai Zhang, Haruhiko Takase, Terumine Hayashi, Hidehiko Kita</I><P>
<DT>
<A HREF="aspabs.htm#02b_4"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
2B.4S A Power Driven Two-Level Logic Optimizer</A>
<DD><I>Jyh-Mou Tseng, Jing-Yang Jou</I><P>
<DT>
<A HREF="aspabs.htm#02b_5"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
2B.5S A Note on the Relationship Between Signal Probability and Switching
Activity</A>
<DD><I>Massoud Pedram, Qing Wu, Xunwei Wu</I><P>
</DL>
<HR>
<H2>Session 2C : <A HREF="aspabs.htm#sess2c" NAME="sess2c">
Timing-Driven Layout
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#02c_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
2C.1 Modeling and Layout Optimization of VLSI Devices and Interconnects in
Deep Submicron Design</A>
<DD><I>Jason Cong</I><P>
<DT>
<A HREF="aspabs.htm#02c_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
2C.2 A New Layout-Driven Timing Model for Incremental Layout Optimization</A>
<DD><I>Fang-Jou Liu, John Lillis, Chung-Kuan Cheng</I><P>
<DT>
<A HREF="aspabs.htm#02c_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
2C.3 Par-POPINS: A Timing-Driven Parallel Placement Method with the Elmore
Delay Model for Row Based VLSIs</A>
<DD><I>Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru
</I><P>
</DL>
<HR>
<H2> <A NAME="sess2d"> Session 2D : Invited Talk</A></H2>
<DL>
<A HREF="aspabs.htm#sess2d"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
Java<SUP>TM</SUP> in Electronic Design Automation</A>
<DD><I>Pete Denyer, Jean Brouwers</I><P>
</DL>
<HR>
<H2>Session 3A : <A HREF="aspabs.htm#sess3a" NAME="sess3a">
Co-Design Experience
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#03a_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
3A.1 Polling-based Real-time Software for MPEG2 System Protocol LSIs
</A>
<DD><I>Jiro Naganuma, Makoto Endo</I><P>
<DT>
<A HREF="aspabs.htm#03a_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
3A.2 Synthesis and Analysis of an Industrial Embedded Microcontroller</A>
<DD><I>Ing-Jer Huang, Li-Rong Wang, Yu-Min Wang</I><P>
<DT>
<A HREF="aspabs.htm#03a_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
3A.3 ASAver.1: An FPGA-Based Education Board for Computer Architecture/System
Design</A>
<DD><I>Hiroyuki Ochi</I><P>
</DL>
<HR>
<H2>Session 3B : <A HREF="aspabs.htm#sess3b" NAME="sess3b">
Design Verification -- Case Studies
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#03b_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
3B.1 Property Verification in the Design of Telecom Applications</A>
<DD><I>M. Bombana, P. Cavalloro, F. Ferrandi</I><P>
<DT>
<A HREF="aspabs.htm#03b_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
3B.2 Verification Methodology of Compatible Microprocessors</A>
<DD><I>Joon-Seo Yim, Chang-Jae Park, Woo-Seung Yang, Hun-Seung Oh,
Hee-Choul Lee, Hoon Choi, Tae-Hoon Kim, Seung-Jong Lee, Nara Won, Yung-Hee Lee,
In-Cheol Park, Chong-Min Kyung</I><P>
<DT>
<A HREF="aspabs.htm#03b_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
3B.3 RTL Verification of Timed Asynchronous and Heterogeneous Systems
using Symbolic Model Checking</A>
<DD><I>Peter A. Beerel, Vida Vakilotojar</I><P>
</DL>
<HR>
<H2>Session 3C : <A HREF="aspabs.htm#sess3c" NAME="sess3c">
Circuit Modeling
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#03c_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
3C.1 CB-Power: A Hierarchical Cell-Based Power Characterization and Estimation
Environment for Static CMOS Circuits</A>
<DD><I>Wen-Zen Shen, Jiing-Yuan Lin, Jyh-Ming Lu</I><P>
<DT>
<A HREF="aspabs.htm#03c_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
3C.2 Power Consumption in CMOS Combinational Logic Blocks at High
Frequencies</A>
<DD><I>Sri Parameswaran, Hui Guo</I><P>
<DT>
<A HREF="aspabs.htm#03c_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
3C.3 A New Approach for an AHDL Based on System Semantics</A>
<DD><I>Youcef Bourai, Nouma Izeboudjen, Yacine Bouhabel, Amine Tafat</I><P>
</DL>
<HR>
<H2><A NAME="sess3d">Session 3D : Special Session - Printed Circuit Board
(PCB) Design and Electro-magnetic Compatibility</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#03d_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
3D.1 EMC-Adequate Design of Printed Circuit Board as a Part of the System
Development</A>
<DD><I> W. John</I><P>
<DT>
<A HREF="aspabs.htm#03d_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
3D.2 Multi-Pride: A System for Supporting Multi-Layered Printed Wiring
Board Design</A>
<DD><I>Toshimasa Watanabe</I><P>
<DT>
<A HREF="aspabs.htm#03d_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
3D.3 Crosstalk Noise in High Density and High Speed Interconnections
due to Inductive Coupling</A>
<DD><I>Tetsuhisa Mido, Kunihiro Asada</I><P>
</DL>
<HR>
<DL>
<H2><A NAME="keynote2">Keynote Address II: </A></H2>
<A HREF="aspabs.htm#keynote2"><IMG SRC="../../../../absicon.gif"></A>
CAD Methodology and Business Models for Future Products</A>
<DD><I> Daniel D. Gajski</I><P>
</DL>
<HR>
<H2>Session 4A : <A HREF="aspabs.htm#sess4a" NAME="sess4a">
Analysis and Trade-Offs in System Synthesis
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#04a_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
4A.1 Embedded Architectural Simulation within Behavioral Synthesis Environment</A>
<DD><I>A. Jemai, P. Kission, A.A. Jerraya</I><P>
<DT>
<A HREF="aspabs.htm#04a_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
4A.2 Evaluating Cost-Performance Tradeoffs for System Level Applications</A>
<DD><I>Wek-Liang Ing, Cheng-Tsung Hwang, Allen Chung-Hao Wu</I><P>
<DT>
<A HREF="aspabs.htm#04a_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
4A.3 A Quantitative Analysis for Optimizing Memory Allocation</A>
<DD><I>Youn-Sik Hong, Choong-Hee Cho, Daniel D. Gajski</I><P>
</DL>
<HR>
<H2>Session 4B : <A HREF="aspabs.htm#sess4b" NAME="sess4b">
Technology Mapping
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#04b_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
4B.1 Concurrent Cell Generation and Mapping for CMOS Logic Circuits</A>
<DD><I>Mineo Kaneko, Jialin Tian</I><P>
<DT>
<A HREF="aspabs.htm#04b_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
4B.2 Logic Synthesis for Cellular Architecture FPGAs Using BDDs</A>
<DD><I>Gueesang Lee</I><P>
<DT>
<A HREF="aspabs.htm#04b_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
4B.3 BDD Based Lambda Set Selection in Roth-Karp Decomposition for LUT
Architecture</A>
<DD><I>Jie-Hong Jiang, Jing-Yang Jou, Juinn-Dar Huang, Jung-Shian Wei</I><P>
</DL>
<HR>
<H2>Session 4C : <A HREF="aspabs.htm#sess4c" NAME="sess4c">
Floorplanning and Placement
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#04c_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
4C.1 General Floorplanning with L-shaped, T-shaped and Soft Blocks Based on
Bounded Slicing Grid Structure</A>
<DD><I>Maggie Kang, Wayne Wei-Ming Dai</I><P>
<DT>
<A HREF="aspabs.htm#04c_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
4C.2 A Building Block Placement Tool</A>
<DD><I>Jonathan Dufour, Robert McBride, Ping Zhang, Chung-Kuan Cheng</I><P>
<DT>
<A HREF="aspabs.htm#04c_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
4C.3S VEAP: Global Optimization based Efficient Algorithm for VLSI Placement</A>
<DD><I>Kong Tianming, Hong Xianlong, Qiao Changge</I><P>
<DT>
<A HREF="aspabs.htm#04c_4"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
4C.4S An Improved Objective for Cell Placement</A>
<DD><I>Yu-Wen Tsay, Hsiao-Pin Su, Youn-Long Lin</I><P>
</DL>
<HR>
<H2>Session 4D : <A HREF="aspabs.htm#sess4d" NAME="sess4d">
(Special Session) University LSI Design Contest Presentation
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#04d_01"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
4D.1P HK386: An x86-Compatible 32bit CICS Microprocessor</A>
<DD><I>C.M. Kyung, I.C. Park, S.K. Hong, K.S. Seong, B.S. Kong, S.J. Lee,
H. Choi, S.R. Maeng, D.T. Kim, J.S. Kim, S.H. Park, Y.J. Kang</I><P>
<DT>
<A HREF="aspabs.htm#04d_02"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
4D.2P Super Low Power 8-bit CPU with Pass-Transistor Logic</A>
<DD><I>Kazuo Taki, Bu-Yeol Lee, Hideki Tanaka, Kenzo Konishi</I><P>
<DT>
<A HREF="aspabs.htm#04d_03"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
4D.3P A Functional Memory Type Parallel Processor for Vector Quantization</A>
<DD><I>K. Kobayashi, M. Kinoshita, M. Takeuchi, H. Onodera, K. Tamaru </I><P>
<DT>
<A HREF="aspabs.htm#04d_04"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
4D.4P High Speed Bit-Serial Parallel Processing on Array Architecture</A>
<DD><I>Kazuhito Ito, Takenobu Shimizugashira, Hiroaki Kunieda</I><P>
<DT>
<A HREF="aspabs.htm#04d_05"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
4D.5P Self-Timed 1-D ICT Processor</A>
<DD><I>Johnson T.C. Pang, Oliver C.S. Choy, C.F. Chan, W.K. Cham
</I><P>
<DT>
<A HREF="aspabs.htm#04d_06"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
4D.6P A Real-Time High Performance Edge Detector for Computer Vision
Applications</A>
<DD><I>Fahad Alzahrani, Tom Chen</I><P>
<DT>
<A HREF="aspabs.htm#04d_07"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
4D.7P An LSI Implementation of the Simple Serial Synchronized Multistage
Interconnection Network</A>
<DD><I>Takayuki Kamei, Masashi Sasahara, Hideharu Amano</I><P>
<DT>
<A HREF="aspabs.htm#04d_08"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
4D.8P The DRT Network Router Chip</A>
<DD><I>Hiroaki Nishi, Hideharu Amano, Katsunobu Nishimura, Ken-ichiro Anjo,
Tomohiro Kudoh</I><P>
<DT>
<A HREF="aspabs.htm#04d_09"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
4D.9P Single Cycle Access Cache for the Misaligned Data and Instruction Prefetch</A>
<DD><I>Joon-Seo Yim, Hee-Choul Lee, Tae-Hoon Kim, Bong-Il Park,
Chang-Jae Park, In-Cheol Park, Chong-Min Kyung</I><P>
<DT>
<A HREF="aspabs.htm#04d_10"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
4D.10P VLSI Implementation of a Real-time Operating System </A>
<DD><I>Takumi Nakano, Yoshiki Komatsudaira, Akichika Shiomi, Masaharu Imai</I><P>
<DT>
<A HREF="aspabs.htm#04d_11"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
4D.11P A CMOS Delayed Locked Loop (DLL) for Reducing Clock Skew to Under
500ps</A>
<DD><I>Yong-Bin Kim, Tom Chen</I><P>
<DT>
<A HREF="aspabs.htm#04d_12"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
4D.12P A Current Mode Cyclic A/D Converter with a 0.8um CMOS Process</A>
<DD><I>Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru</I><P>
<DT>
<A HREF="aspabs.htm#04d_13"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
4D.13P A Current-mode,3V,20MHz, 9-bit equivalent CMOS Sample-and-Hold
Circuit</A>
<DD><I>Yasuhiro Sugimoto, Tetsuya Iida</I><P>
</DL>
<HR>
<H2>Session 5A : <A HREF="aspabs.htm#sess5a" NAME="sess5a">
Co-Design: Architecture and Partitioning
</A></H2>
<DT>
<A HREF="aspabs.htm#05a_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
5A.1 Hardware-Software Co-design: Tools for Architecting Systems-On-A-Chip </A>
<DD><I>Rajesh K. Gupta</I><P>
<DT>
<A HREF="aspabs.htm#05a_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
5A.2 Trade-off Evaluation in Embedded System Design Via Co-simulation</A>
<DD><I>Claudio Passerone, Luciano Lavagno, Claudio Sansoe, Massimiliano Chiodo, Alberto Sangiovanni-Vincentelli</I><P>
<DT>
<A HREF="aspabs.htm#05a_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
5A.3 A Transformational Codesign Methodology</A>
<DD><I>Tommy King-Yin Cheung, Graham Hellestrand, Prasert Kanthamanon</I><P>
</DL>
<HR>
<H2>Session 5B : <A HREF="aspabs.htm#sess5b" NAME="sess5b">
Hierarchical/High-Level Testing
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#05b_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
5B.1 A Testability Analysis Method for Register-Transfer Level Descriptions
</A>
<DD><I>Mizuki Takahashi, Ryoji Sakurai, Hiroaki Noda, Takashi Kambe</I><P>
<DT>
<A HREF="aspabs.htm#05b_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
5B.2 Non-Scan Design for Testable Data Paths Using Thru Operation</A>
<DD><I>Katsuyuki Takabatake, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara</I><P>
<DT>
<A HREF="aspabs.htm#05b_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
5B.3 Block-Level Fault Isolation Using Partition Theory and Logic Minimization
Techniques</A>
<DD><I>C.-J. Richard Shi</I><P>
<DT>
<A HREF="aspabs.htm#05b_4"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
5B.4S The Use of Hierarchical Information to Test Large Controllers</A>
<DD><I>F. Fummi, D. Sciuto</I><P>
<DT>
<A HREF="aspabs.htm#05b_5"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
5B.5S Hierarchical Fault Tracing for VLSI Sequential Circuits from CAD
Layout Data in the CAD-linked EB Test System</A>
<DD><I>Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka</I><P>
</DL>
<HR>
<H2>Session 5C : <A HREF="aspabs.htm#sess5c" NAME="sess5c">
Technology Related Issues
</A></H2>
<DL>
<DT>
5C.1 Interconnect Capacitances, Crosstalk, and Signal Delay in High Speed
and High Density VLSI Circuits (No Paper Submitted)
<DD><I>D.H. Cho, M.H. Seung, N.H. Kim, H.S. Park</I><P>
<DT>
<A HREF="aspabs.htm#05c_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
5C.2 Monte Carlo Simulation for Single Electron Circuits</A>
<DD><I>Masaharu Kirihara, Kenji Taniguchi</I><P>
<DT>
<A HREF="aspabs.htm#05c_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
5C.3 Parallel Calculation of 3-D Parasitic Resistance and Capacitance
with Linear Boundary Elements</A>
<DD><I>Wenming Zhou, Zeyi Wang, Lan Rao</I><P>
<DT>
<A HREF="aspabs.htm#05c_4"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
5C.4 Simulation of Gate Switching Characteristics of a Miniaturized MOSFET
based on a Non-Isothermal Non-Equilibrium Transport Model</A>
<DD><I>Won-Cheol Choi, Hirobumi Kawahima, Ryo Dang</I><P>
</DL>
<HR>
<H2><A NAME="sess5d">Session 5D :
(Special Session) Multiproject Chip Services in Asia and the South Pacific
</A></H2>
<I> Moderator :Hideharu Amano(Keio Univ.,) and Tokinori Kozawa(STARC)<BR>
Chairperson : Kazuhiro Ueda (Shibaura Institute of Technology)<P>
</I>
Presented by : <P>
<DL>
<DT>
<A HREF="aspabs.htm#05d_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
The EUROPRACTICE MPC Service</A>
<DD><I>C. Das</I><P>
<DT>
<A HREF="aspabs.htm#05d_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
Multi-Project Chip Activities in Korea-IDEC Perspective-</A>
<DD><I>Chong-Min Kyung, In-Cheol Park, Ho-Jun Song</I><P>
<DT>
<A HREF="aspabs.htm#05d_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
Multi-Project Chip Service for University and Industry in Taiwan</A>
<DD><I>Jen-Sheng Hwang</I><P>
<DT>
<A HREF="aspabs.htm#05d_4"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
VLSI Design and Education Center (VDEC) Current Status and Future Plan </A>
<DD><I>Kunihiro Asada and Koichiro Hoh</I><P>
</DL>
<HR>
<H2>Session 6A : <A HREF="aspabs.htm#sess6a" NAME="sess6a">
Simulation Environment
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#06a_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
6A.1 Choosing a Digital Simulator</A>
<DD><I>John Hillawi</I><P>
<DT>
<A HREF="aspabs.htm#06a_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
6A.2 A Hardware/Software Co-simulation Environment for Micro-processor
Design with HDL Simulator and OS interface</A>
<DD><I>Yoshiyuki Ito, Yuichi Nakamura</I><P>
<DT>
<A HREF="aspabs.htm#06a_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
6A.3S VIDE: A Visual VHDL Integrated Design Environment</A>
<DD><I>Jinian Bian, Hongxi Xue, Ming Su</I><P>
<DT>
<A HREF="aspabs.htm#06a_4"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
6A.4S Advanced Processor Design using Hardware Description Language AIDL</A>
<DD><I>Takayuki Morimoto, Kazushi Saito, Hiroshi Nakamura, Taisuke Boku,
Kisaburo Nakazawa</I><P>
</DL>
<HR>
<H2>Session 6B : <A HREF="aspabs.htm#sess6b" NAME="sess6b">
Testing for Non-Conventional Fault Models
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#06b_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
6B.1 Adaptive Models for Input Data Compaction for Power Simulators</A>
<DD><I>Radu Marculescu, Diana Marculescu, Massoud Pedram</I><P>
<DT>
<A HREF="aspabs.htm#06b_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
6B.2S Fuzzy-based Circuit Partitioning in Built-in Current Testing</A>
<DD><I>Wang-Dauh Tseng, Kuochen Wang</I><P>
<DT>
<A HREF="aspabs.htm#06b_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
6B.3S Reducing the Complexity of Path Classification by Reconvergence Analysis</A>
<DD><I>Paul Tafertshofer, Andreas Ganz, Manfred Henftling</I><P>
<DT>
<A HREF="aspabs.htm#06b_4"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
6B.4S Modelling and Detection of Dynamic Errors due to Reflection - and
Crosstalk-Noise</A>
<DD><I>J. Schrage</I><P>
<DT>
<A HREF="aspabs.htm#06b_5"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
6B.5S Fault Coverage Improvement Based on Error Signal Analysis</A>
<DD><I>Mike W.T. Wong, Y. Zhou, Y.S. Lee, Y. Min</I><P>
</DL>
<HR>
<H2>Session 6C : <A HREF="aspabs.htm#sess6c" NAME="sess6c">
Circuit Design and Methodology
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#06c_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
6C.1 Low-Power Multiple-Valued Current-Mode Integrated Circuit with
Current-Source Control and Its Application</A>
<DD><I>Takahiro Hanyu, Satoshi Kazama, Mitchitaka Kameyama</I><P>
<DT>
<A HREF="aspabs.htm#06c_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
6C.2 Analysis and Design of Multiple-Bit High-Order E-^ Modulator</A>
<DD><I>Hao-Chiao Hong, Bin-Hong Lin, Cheng-Wen Wu</I><P>
<DT>
<A HREF="aspabs.htm#06c_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
6C.3S Optimal Loop Bandwidth Design for Low Noise PLL Applications</A>
<DD><I>Kyoohyun Lim, Seunghee Choi, BeomSup Kim</I><P>
<DT>
<A HREF="aspabs.htm#06c_4"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
6C.4S +-1.5V CMOS Four-Quadrant Multiplier</A>
<DD><I>Simon C. Li</I><P>
</DL>
<HR>
<H2>Session 6D : <A HREF="aspabs.htm#sess6d" NAME="sess6d">
(Panel Discussion)Collaboration between University and Industry
</A></H2>
<I>Moderator : Tokinori Kozawa (STARC)<BR>
Chair : Tokinori Kozawa (STARC, Japan)<P>
Panelist :
<UL>
<LI>Ralph Cavin (SRC,USA)<BR>
<LI> Paul Six (IMEC, Belgium)<BR>
<LI> Taro Okabe (STARC, Japan)<BR>
<LI> Akihiko Morino (NEC,Japan)<BR>
<LI> Hiroto Yasuura (Kyushu Univ., Japan)<BR>
<LI> Youn-Long Lin (Ting-Hua Univ., Taiwan)<BR>
</UL>
</I><P>
<HR>
<DL>
<H2><A NAME="keynote3">Keynote Address III: </A></H2>
<A HREF="aspabs.htm#keynote3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
Some Thoughts on Process Retargettable and Reusable IC Intellectual
Property</A>
<DD><I>Neil Weste</I><P>
</DL>
<HR>
<H2>Session 7A : <A HREF="aspabs.htm#sess7a" NAME="sess7a">
High-Level Synthesis Techniques for FPGA's and Regular Arrays
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#07a_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
7A.1 ChipEst-FPGA: A Tool for Chip Level Area and Timing Estimation of Lookup
Table Based FPGAs for High Level Applications</A>
<DD><I>Min Xu, Fadi Kurdahi</I><P>
<DT>
<A HREF="aspabs.htm#07a_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
7A.2 Bit-Serial Pipeline Synthesis and Layout for Large-Scale Configurable
Systems</A>
<DD><I>Tsuyoshi Isshiki, Wayne Wei-Ming Dai, Hiroaki Kunieda</I><P>
<DT>
<A HREF="aspabs.htm#07a_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
7A.3 An Optimal Scheduling Method for Parallel Processing System of Array
Architecture</A>
<DD><I>Kazuhito Ito, Tadashi Iwata, Hiroaki Kunieda</I><P>
</DL>
<HR>
<H2>Session 7B : <A HREF="aspabs.htm#sess7b" NAME="sess7b">
Decision Diagrams and Their Applications
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#07b_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
7B.1 AQUILA: An Equivalence Verifier for Large Sequential Circuits</A>
<DD><I>Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen</I><P>
<DT>
<A HREF="aspabs.htm#07b_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
7B.2 On the Representational Power of Bit-Level and Word-Level Decision
Diagrams</A>
<DD><I>Bernd Becker, Rolf Drechsler, Reinhard Enders</I><P>
<DT>
<A HREF="aspabs.htm#07b_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
7B.3S Learning Heuristics for OKFDD Minimization by Evolutionary Algorithms</A>
<DD><I>Nicole Göckel, Rolf Drechsler, Bernd Becker</I><P>
<DT>
<A HREF="aspabs.htm#07b_4"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
7B.4S On Properties of Kleene TDDs</A>
<DD><I>Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura</I><P>
</DL>
<HR>
<H2>Session 7C : <A HREF="aspabs.htm#sess7c" NAME="sess7c">
Circuit Analysis and Simulation
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#07c_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
7C.1 A Time-Domain Method for Numerical Noise Analysis of Oscillators</A>
<DD><I>Makiko Okumura, Hiroshi Tanimoto</I><P>
<DT>
<A HREF="aspabs.htm#07c_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
7C.2 A New Linear-Time Harmonic Balance Algorithm for Cyclostationary
Noise Analysis in RF Circuits</A>
<DD><I>J.S. Roychowdhury, Peter Feldmann</I><P>
<DT>
<A HREF="aspabs.htm#07c_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
7C.3 Enhancement of Parallelism for Tearing-based Circuit Simulation</A>
<DD><I>Koutaro Hachiya, Toshiyuki Saito, Toshiyuki Nakata, Norio Tanabe</I><P>
</DL>
<HR>
<DL>
<H2>Session 7D: <A NAME="sess7d">Tutorial </A></H2>
<A HREF="aspabs.htm#sess7d"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
Design and Test of Processor-Core Based Sytems</A>
<DD><I>Peter Marwedel</I><P>
</DL>
<HR>
<H2>Session 8A : <A HREF="aspabs.htm#sess8a" NAME="sess8a">
Estimation from High-Level/RTL Descriptions</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#08a_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
8A.1 Architecture Evaluation Based on the Datapath Structure and Parallel Constraint </A>
<DD><I>Masayuki Yamaguchi, Akihisa Yamada, Toshihiro Nakaoka, Takashi Kambe</I><P>
<DT>
<A HREF="aspabs.htm#08a_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
8A.2 A Constructive Method for Data Path Area Estimation During High-Level VLSI
Synthesis</A>
<DD><I>V. Natesan, Anurag Gupta, Srinivas Katkoori, Dinesh Bhatia, Ranga Vemuri</I><P>
<DT>
<A HREF="aspabs.htm#08a_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
8A.3 RT Level Power Analysis</A>
<DD><I>Jianwen Zhu, Poonam Agrawal, Daniel D. Gajski</I><P>
<DT>
<A HREF="aspabs.htm#08a_4"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
8A.4 Statistical Design of Macro-models For RT-level Power Evaluation</A>
<DD><I>Qing Wu, Chihshun Ding, Chengtah Hsieh, Massoud Pedram</I><P>
</DL>
<HR>
<H2>Session 8B : <A HREF="aspabs.htm#sess8b" NAME="sess8b">
Logic Synthesis and Modeling
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#08b_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
8B.1 AND/OR Reasoning Graphs for Determining Prime Implicants in
Multi-Level Combinational Networks</A>
<DD><I>Dominik Stoffel, Wolfgang Kunz, Stefan Gerber</I><P>
<DT>
<A HREF="aspabs.htm#08b_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
8B.2 Efficient Synthesis of AND/XOR Networks</A>
<DD><I>Yibin Ye, Kaushik Roy</I><P>
<DT>
<A HREF="aspabs.htm#08b_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm" AME="sess8b">
8B.3 An Optimization of AND-OR-EXOR Three-level Networks</A>
<DD><I>Debatosh Debnath, Tsutomu Sasao</I><P>
<DT>
<A HREF="aspabs.htm#08b_4"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
8B.4 A New Description of CMOS Circuits at Switch-Level</A>
<DD><I>Xunwei Wu, Massoud Pedram</I><P>
</DL>
<HR>
<H2>Session 8C : <A HREF="aspabs.htm#sess8c" NAME="sess8c">
Module Generation and FPGA Layout
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#08c_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
8C.1 A 2-Dimensional Transistor Placement for Cell Synthesis</A>
<DD><I>Shunji Saika, Masahiro Fukui, Noriko Shinomiya, Toshira Akino</I><P>
<DT>
<A HREF="aspabs.htm#08c_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
8C.2 DP-Gen: A Datapath Generator for Multiple-FPGA Applications</A>
<DD><I>Wen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen, Tsair-Chin Lin</I><P>
<DT>
<A HREF="aspabs.htm#08c_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
8C.3 A Simultaneous Placement and Global Routing Algorithm with Path
Length Constraints for Transport-Processing FPGAs</A>
<DD><I>Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki</I><P>
<DT>
<A HREF="aspabs.htm#08c_4"><IMG SRC="../../../../absicon.gif"></A>
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8C.4 Not Necessarily More Switches More Routability</A>
<DD><I>Yu-Liang Wu, Douglas Chang, Malgorzata Marek-Sadowska, Shuji Tsukiyama</I><P>
</DL>
<HR>
<H2>Session 8D : <A NAME="sess8d">(Panel Discussion) Design Standardization for 2001</A></H2>
<B>The SEMATECH Chip Hierarchical Design System - new paradigms for deep
submicron design</B><BR>
<I>Invited Talk: Greg Ledenbach</I><P>
<B>Panel : EDA Standardization including CHDS</B><BR>
<I>Moderator : Hitoshi Yoshizawa, NEC<BR>
Organizer: Hisakazu Edamatsu, Matsushita Electric Industrial</I><BR><P>
<B>Panel: The Role of Design Standardization in future complex design</B><P>
<HR>
<H2>Session 9A : <A HREF="aspabs.htm#sess9a" NAME="sess9a">
Aspects of Hardware and Software Synthesis
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#09a_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
9A.1 On the Control-subroutine Implementation of Subprogram Synthesis</A>
<DD><I>Cheng-Tsung Hwang, Hsiao-Cheng Weng, Yu-Chin Hsu, Mike Tien-Chien Lee
</I><P>
<DT>
<A HREF="aspabs.htm#09a_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
9A.2 A Procedure for Software Synthesis from VHDL Models</A>
<DD><I>Venkatram Krishnaswamy, Rajesh K. Gupta, Prithviraj Banerjee</I><P>
<DT>
<A HREF="aspabs.htm#09a_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
9A.3 Built-in Chaining: Introducing Complex Components into Architectural
Synthesis</A>
<DD><I>Peter Marwedel, Birger Landwehr, Rainer Dömer</I><P>
</DL>
<HR>
<H2>Session 9B : <A HREF="aspabs.htm#sess9b" NAME="sess9b">
Sequential Synthesis
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#09b_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
9B.1 BDD-based Logic Partitioning for Sequential Circuits</A>
<DD><I>Ming-Ter Kuo, Yifeng Wang, Chung-Kuan Cheng, Masahiro Fujita</I><P>
<DT>
<A HREF="aspabs.htm#09b_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
9B.2 Cube-Embedding Based State Encoding for Low Power Design</A>
<DD><I>De-Sheng Chen, Majid Sarrafzadeh</I><P>
<DT>
<A HREF="aspabs.htm#09b_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
9B.3 On Synthesis of Speed-Independent Circuits at STG Level</A>
<DD><I>Kuan-Jen Lin, Chi-Wen Kuo</I><P>
</DL>
<HR>
<H2>Session 9C : <A HREF="aspabs.htm#sess9c" NAME="sess9c">
Theoretical Aspects of Layout Design
</A></H2>
<DL>
<DT>
<A HREF="aspabs.htm#09c_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
9C.1 A Mapping from Sequence-Pair to Rectangular Dissection</A>
<DD><I>Hiroshi Murata, Kunihiro Fujiyoshi, Tomomi Watanabe, Yoji Kajitani</I><P>
<DT>
<A HREF="aspabs.htm#09c_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
9C.2 Solving Constrained Via Minimization by Compact Linear Programming</A>
<DD><I>C.-J. Richard Shi</I><P>
<DT>
<A HREF="aspabs.htm#09c_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
9C.3S Efficient Routability Checking for Global Wires in Planar Layouts</A>
<DD><I>Naoyuki Iso, Yasushi Kawaguchi, Tomio Hirata</I><P>
<DT>
<A HREF="aspabs.htm#09c_4"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
9C.4S Topological Routing Path Search Algorithm with Incremental Routability
Test</A>
<DD><I>Toshiyuki Hama, Hiroaki Etoh</I><P>
</DL>
<HR>
<H2>Session 9D : Tutorial <A HREF="aspabs.htm#sess9d" NAME="sess9d"></H2>
<DL>
<A HREF="aspabs.htm#09d_0"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
VHDL Analog and Mixed-Signal Extensions Through Examples</A><BR>
<DD><I>Alain Vachoux</I>
</DL>
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