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<H3><A HREF="../../../../../main_ss.htm">ASPDAC 97 Home Page</A></BR>
ASPDAC 97 :
[ <A HREF="asptoc.htm">Table of Contents</A> ]
[ <A HREF="aspabs.htm">Abstracts</A> ]
[ <A HREF="aspai.htm">Author Index</A> ]</H3>
<HR>
<H2>SESSION INDEX ASPDAC 97</H2>
<B>
Keynote Address I:
<A HREF="aspabs.htm#keynote1">
Microelectronics Evolution Brings Real Multimedia Era</A><BR>
Session 1A : <A HREF="aspabs.htm#sess1a">
Rapid Prototyping
</A><BR>
Session 1B : <A HREF="aspabs.htm#sess1b">
Delay Estimation and Optimization
</A><BR>
Session 1C : <A HREF="aspabs.htm#sess1c">
Circuit Partitioning
</A><BR>
Session 1D : <A HREF="aspabs.htm#sess1d">
(Invited Talk) Computing Brokerage and Its Applications in VLSI Design
</A><BR>
Session 2A : <A HREF="aspabs.htm#sess2a">
Application Specific Design
</A><BR>
Session 2B : <A HREF="aspabs.htm#sess2b">
Power: Estimation and Synthesis
</A><BR>
Session 2C : <A HREF="aspabs.htm#sess2c">
Timing-Driven Layout
</A><BR>
Session 2D : <A HREF="aspabs.htm#sess2d">
Invited Talk : Java<SUP>TM</SUP> in Electronic Design Automation
</A><BR>
Session 3A : <A HREF="aspabs.htm#sess3a">
Co-Design Experience
</A><BR>
Session 3B : <A HREF="aspabs.htm#sess3b">
Design Verification -- Case Studies
</A><BR>
Session 3C : <A HREF="aspabs.htm#sess3c">
Circuit Modeling
</A><BR>
Sission 3D : <A HREF="aspabs.htm#sess3d">
Special Session - Printed Circuit Board
(PCB) Design and Electro-magnetic Compatibility
</A><BR>
Keynote Address II: <A HREF="aspabs.htm#keynote2">
CAD Methodology and Business Models for Future Products
</A><BR>
Session 4A : <A HREF="aspabs.htm#sess4a">
Analysis and Trade-Offs in System Synthesis
</A><BR>
Session 4B : <A HREF="aspabs.htm#sess4b">
Technology Mapping
</A><BR>
Session 4C : <A HREF="aspabs.htm#sess4c">
Floorplanning and Placement
</A><BR>
Session 4D : <A HREF="aspabs.htm#sess4d">
(Special Session) University LSI Design Contest Presentation
</A><BR>
Session 5A : <A HREF="aspabs.htm#sess5a">
Co-Design: Architecture and Partitioning
</A><BR>
Session 5B : <A HREF="aspabs.htm#sess5b">
Hierarchical/High-Level Testing
</A><BR>
Session 5C : <A HREF="aspabs.htm#sess5c">
Technology Related Issues
</A><BR>
Session 5D : <A HREF="aspabs.htm#sess5d">
(Special Session) Multiproject Chip Services in Asia and the South Pacific
</A><BR>
Session 6A : <A HREF="aspabs.htm#sess6a">
Simulation Environment
</A><BR>
Session 6B : <A HREF="aspabs.htm#sess6b">
Testing for Non-Conventional Fault Models
</A><BR>
Session 6C : <A HREF="aspabs.htm#sess6c">
Circuit Design and Methodology
</A><BR>
Session 6D : <A HREF="aspabs.htm#sess6d">
(Panel Discussion)Collaboration between University and Industry
</A><BR>
Keynote Address III: <A HREF="aspabs.htm#keynote3">
Some Thoughts on Process Retargettable and Reusable IC Intellectual
Property
</A><BR>
Session 7A : <A HREF="aspabs.htm#sess7a">
High-Level Synthesis Techniques for FPGA's and Regular Arrays
</A><BR>
Session 7B : <A HREF="aspabs.htm#sess7b">
Decision Diagrams and Their Applications
</A><BR>
Session 7C : <A HREF="aspabs.htm#sess7c">
Circuit Analysis and Simulation
</A><BR>
Session 7D : <A HREF="aspabs.htm#sess7d">
(Tutorial) Design and Test of Processor-Core Based Sytems
</A><BR>
Session 8A : <A HREF="aspabs.htm#sess8a">
Estimation from High-Level/RTL Descriptions
</A><BR>
Session 8B : <A HREF="aspabs.htm#sess8b">
Logic Synthesis and Modeling
</A><BR>
Session 8C : <A HREF="aspabs.htm#sess8c">
Module Generation and FPGA Layout
</A><BR>
Session 8D : <A HREF="aspabs.htm#sess8d">
(Panel Discussion) Design Standardization for 2001
</A><BR>
Session 9A : <A HREF="aspabs.htm#sess9a">
Aspects of Hardware and Software Synthesis
</A><BR>
Session 9B : <A HREF="aspabs.htm#sess9b">
Sequential Synthesis
</A><BR>
Session 9C : <A HREF="aspabs.htm#sess9c">
Theoretical Aspects of Layout Design
</A><BR>
Session 9D : <A HREF="aspabs.htm#sess9d">
Tutorial: VHDL Analog and Mixed-Signal Extensions Through Examples
</A><BR>
</B>
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