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ASPDAC 97 :
[ <A HREF="asptoc.htm">Table of Contents</A> ]
[ <A HREF="aspabs.htm">Abstracts</A> ]
[ <A HREF="aspsess.htm">Session Index</A> ]</H3>
<HR>
<H2>AUTHOR INDEX ASPDAC 97</H2>
<B>
<A HREF="#A">[A]</A>
<A HREF="#B">[B]</A>
<A HREF="#C">[C]</A>
<A HREF="#D">[D]</A>
<A HREF="#E">[E]</A>
<A HREF="#F">[F]</A>
<A HREF="#G">[G]</A>
<A HREF="#H">[H]</A>
<A HREF="#I">[I]</A>
<A HREF="#J">[J]</A>
<A HREF="#K">[K]</A>
<A HREF="#L">[L]</A>
<A HREF="#M">[M]</A>
<A HREF="#N">[N]</A>
<A HREF="#O">[O]</A>
<A HREF="#P">[P]</A>
<A HREF="#R">[R]</A>
<A HREF="#S">[S]</A>
<A HREF="#T">[T]</A>
<A HREF="#V">[V]</A>
<A HREF="#W">[W]</A>
<A HREF="#X">[X]</A>
<A HREF="#Y">[Y]</A>
<A HREF="#Z">[Z]</A><P>
</B>
<HR>
<DL><H1><A NAME="A">A</A></H1>
<DT><B>Agrawal, P. </B>
<DD><A HREF="aspabs.htm#08a_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> RT Level Power Analysis</I></A>
<DT><B>Akino, T. </B>
<DD><A HREF="aspabs.htm#08c_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> A 2-Dimensional Transistor Placement for Cell Synthesis</I></A>
<DT><B>Alzahrani, F. </B>
<DD><A HREF="aspabs.htm#04d_06"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> A Real-Time High Performance Edge Detector for Computer Vision
Applications</I></A>
<DT><B>Amano, H. </B>
<DD><A HREF="aspabs.htm#04d_07"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> An LSI Implementation of the Simple Serial Synchronized Multistage
Interconnection Network</I></A>
<DD><A HREF="aspabs.htm#04d_08"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> The DRT Network Router Chip</I></A>
<DT><B>Anjo, K.-i. </B>
<DD><A HREF="aspabs.htm#04d_08"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> The DRT Network Router Chip</I></A>
<DT><B>Asada, K. </B>
<DD><A HREF="aspabs.htm#03d_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I>Crosstalk Noise in High Density and High Speed Interconnections
due to Inductive Coupling</I></A>
<DD><A HREF="aspabs.htm#05d_4"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I>VLSI Design and Education Center (VDEC) Current Status and future plan
</I></A>
</DL>
<HR>
<DL><H1><A NAME="B">B</A></H1>
<DT><B>Banerjee, P. </B>
<DD><A HREF="aspabs.htm#09a_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> A Procedure for Software Synthesis from VHDL Models</I></A>
<DT><B>Barke, E. </B>
<DD><A HREF="aspabs.htm#01c_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Design Driven Partitioning</I></A>
<DT><B>Becker, B. </B>
<DD><A HREF="aspabs.htm#07b_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> On the Representational Power of Bit-Level and Word-Level Decision
Diagrams</I></A>
<DD><A HREF="aspabs.htm#07b_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Learning Heuristics for OKFDD Minimization by Evolutionary Algorithms</I></A>
<DT><B>Beerel, P.A. </B>
<DD><A HREF="aspabs.htm#03b_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> RTL Verification of Timed Asynchronous and Heterogeneous Systems
using Symbolic Model Checking</I></A>
<DT><B>Behrens, D. </B>
<DD><A HREF="aspabs.htm#01c_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Design Driven Partitioning</I></A>
<DT><B>Bhatia, D. </B>
<DD><A HREF="aspabs.htm#08a_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> A Constructive Method for Data Path Area Estimation During High-Level VLSI
Synthesis</I></A>
<DT><B>Bian, J. </B>
<DD><A HREF="aspabs.htm#06a_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> VIDE: A Visual VHDL Integrated Design Environment</I></A>
<DT><B>Boku, T. </B>
<DD><A HREF="aspabs.htm#06a_4"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Advanced Processor Design using Hardware Description Language AIDL</I></A>
<DT><B>Bombana, M. </B>
<DD><A HREF="aspabs.htm#03b_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Property Verification in the Design of Telecom Applications</I></A>
<DT><B>Bouhabel, Y. </B>
<DD><A HREF="aspabs.htm#03c_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> A New Approach for an AHDL Based on System Semantics</I></A>
<DT><B>Bourai, Y. </B>
<DD><A HREF="aspabs.htm#03c_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> A New Approach for an AHDL Based on System Semantics</I></A>
<DT><B>Brouwers, J. </B>
<DD><A HREF="aspabs.htm#sess2d"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I>Java<SUP>TM</SUP> in Electronic Design Automation</I></A>
</DL>
<HR>
<DL><H1><A NAME="C">C</A></H1>
<DT><B>Cavalloro, P. </B>
<DD><A HREF="aspabs.htm#03b_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Property Verification in the Design of Telecom Applications</I></A>
<DT><B>Cham, W.K. </B>
<DD><A HREF="aspabs.htm#04d_05"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Self-Timed 1-D ICT Processor</I></A>
<DT><B>Chan, C.F. </B>
<DD><A HREF="aspabs.htm#04d_05"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Self-Timed 1-D ICT Processor</I></A>
<DT><B>Chang, D. </B>
<DD><A HREF="aspabs.htm#08c_4"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Not Necessarily More Switches More Routability</I></A>
<DT><B>Changge, Q. </B>
<DD><A HREF="aspabs.htm#04c_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> VEAP: Global Optimization based Efficient Algorithm for VLSI Placement</I></A>
<DT><B>Chen, D.-S. </B>
<DD><A HREF="aspabs.htm#09b_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Cube-Embedding Based State Encoding for Low Power Design</I></A>
<DT><B>Chen, K.-C. </B>
<DD><A HREF="aspabs.htm#07b_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> AQUILA: An Equivalence Verifier for Large Sequential Circuits</I></A>
<DT><B>Chen, K. Y. </B>
<DD><A HREF="aspabs.htm#02a_4"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Structural Approach for Performance Driven ECC Circuit Synthesis</I></A>
<DT><B>Chen, T. </B>
<DD><A HREF="aspabs.htm#04d_06"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> A Real-Time High Performance Edge Detector for Computer Vision
Applications</I></A>
<DD><A HREF="aspabs.htm#04d_11"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> A CMOS Delayed Locked Loop (DLL) for Reducing Clock Skew to Under
500ps</I></A>
<DT><B>Cheng, C.-K. </B>
<DD><A HREF="aspabs.htm#02c_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> A New Layout-Driven Timing Model for Incremental Layout Optimization</I></A>
<DD><A HREF="aspabs.htm#04c_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> A Building Block Placement Tool</I></A>
<DD><A HREF="aspabs.htm#09b_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> BDD-based Logic Partitioning for Sequential Circuits</I></A>
<DT><B>Cheng, K.-T. </B>
<DD><A HREF="aspabs.htm#07b_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> AQUILA: An Equivalence Verifier for Large Sequential Circuits</I></A>
<DT><B>Cheung, T. K.-Y. </B>
<DD><A HREF="aspabs.htm#05a_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> A Transformational Codesign Methodology</I></A>
<DT><B>Chiodo, M. </B>
<DD><A HREF="aspabs.htm#05a_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Trade-off Evaluation in Embedded System Design Via Co-simulation</I></A>
<DT><B>Cho, C.-H. </B>
<DD><A HREF="aspabs.htm#04a_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> A Quantitative Analysis for Optimizing Memory Allocation</I></A>
<DT><B>Cho, D.H. </B><BR>
<DD><I> Interconnect Capacitances, Crosstalk, and Signal Delay in High Speed
and High Density VLSI Circuits (No Paper Submitted)</I>
<DT><B>Choi, H. </B>
<DD><A HREF="aspabs.htm#03b_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Verification Methodology of Compatible Microprocessors</I></A>
<DD><A HREF="aspabs.htm#04d_01"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> HK386: An x86-Compatible 32bit CICS Microprocessor</I></A>
<DT><B>Choi, S. </B>
<DD><A HREF="aspabs.htm#06c_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Optimal Loop Bandwidth Design for Low Noise PLL Applications</I></A>
<DT><B>Choi, W.-C. </B>
<DD><A HREF="aspabs.htm#05c_4"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Simulation of Gate Switching Characteristics on a Miniaturized MOSFET
based on a Non-Isothermal Non-Equilibrium Transport Model</I></A>
<DT><B>Chou, T.-L. </B>
<DD><A HREF="aspabs.htm#02b_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Statistical Estimation of Combinational and Sequential CMOS Digital
Circuit Activity Considering Uncertainty of Gate Delay</I></A>
<DT><B>Choy, O.C.S. </B>
<DD><A HREF="aspabs.htm#04d_05"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Self-Timed 1-D ICT Processor</I></A>
<DT><B>Cong, J. </B>
<DD><A HREF="aspabs.htm#02c_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Modeling and Layout Optimization of VLSI Devices and Interconnects in
Deep Submicron Design</I></A>
</DL>
<HR>
<DL><H1><A NAME="D">D</A></H1>
<DT><B>Dai, W. W.-M. </B>
<DD><A HREF="aspabs.htm#04c_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> General Floorplanning with L-shaped, T-shaped and Soft Blocks Based on
Bounded Slicing Grid Structure</I></A>
<DD><A HREF="aspabs.htm#07a_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Bit-Serial Pipeline Synthesis and Layout for Large-Scale Configurable
Systems</I></A>
<DT><B>Dang, R. </B>
<DD><A HREF="aspabs.htm#05c_4"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Simulation of Gate Switching Characteristics on a Miniaturized MOSFET
based on a Non-Isothermal Non-Equilibrium Transport Model</I></A>
<DT><B>Das, C. </B>
<DD><A HREF="aspabs.htm#05d_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I>The EUROPRACTICE MPC Service</I></A>
<DT><B>Debnath, D. </B>
<DD><A HREF="aspabs.htm#08b_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> An Optimization of AND-OR-EXOR Three-level Networks</I></A>
<DT><B>Denyer, P. </B>
<DD><A HREF="aspabs.htm#sess2d"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I>Java<SUP>TM</SUP> in Electronic Design Automation</I></A>
<DT><B>Ding, C. </B>
<DD><A HREF="aspabs.htm#08a_4"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Statistical Design of Macro-models For RT-level Power Evaluation</I></A>
<DT><B>Dömer, R. </B>
<DD><A HREF="aspabs.htm#09a_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Built-in Chaining: Introducing Complex Components into Architectural
Synthesis</I></A>
<DT><B>Drechsler, R. </B>
<DD><A HREF="aspabs.htm#07b_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> On the Representational Power of Bit-Level and Word-Level Decision
Diagrams</I></A>
<DD><A HREF="aspabs.htm#07b_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Learning Heuristics for OKFDD Minimization by Evolutionary Algorithms</I></A>
<DT><B>Dufour, J. </B>
<DD><A HREF="aspabs.htm#04c_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> A Building Block Placement Tool</I></A>
</DL>
<HR>
<DL><H1><A NAME="E">E</A></H1>
<DT><B>Enders, R. </B>
<DD><A HREF="aspabs.htm#07b_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> On the Representational Power of Bit-Level and Word-Level Decision
Diagrams</I></A>
<DT><B>Endo, M. </B>
<DD><A HREF="aspabs.htm#03a_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Polling-based Real-time Software for MPEG2 System Protocol LSIs
</I></A>
<DT><B>Etoh, H. </B>
<DD><A HREF="aspabs.htm#09c_4"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Topological Routing Path Search Algorithm with Incremental Routability
Test</I></A>
</DL>
<HR>
<DL><H1><A NAME="F">F</A></H1>
<DT><B>Fang, W.-J. </B>
<DD><A HREF="aspabs.htm#08c_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> DP-Gen: A Datapath Generator for Multiple-FPGA Applications</I></A>
<DT><B>Feldmann, P. </B>
<DD><A HREF="aspabs.htm#07c_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> A New Linear-Time Harmonic Balance Algorithm for Cyclostationary
Noise Analysis in RF Circuits</I></A>
<DT><B>Ferrandi, F. </B>
<DD><A HREF="aspabs.htm#03b_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Property Verification in the Design of Telecom Applications</I></A>
<DT><B>Fujioka, H. </B>
<DD><A HREF="aspabs.htm#05b_5"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Hierarchical Fault Tracing for VLSI Sequential Circuits from CAD
Layout Data in the CAD-linked EB Test System</I></A>
<DT><B>Fujita, M. </B>
<DD><A HREF="aspabs.htm#01b_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Delay Estimation on Optimization of Logic Circuits: A Survey</I></A>
<DD><A HREF="aspabs.htm#09b_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> BDD-based Logic Partitioning for Sequential Circuits</I></A>
<DT><B>Fujiwara, H. </B>
<DD><A HREF="aspabs.htm#05b_2"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Non-Scan Design for Testable Data Paths Using Thru Operation</I></A>
<DT><B>Fujiyoshi, K. </B>
<DD><A HREF="aspabs.htm#09c_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> A Mapping from Sequence-Pair to Rectangular Dissection</I></A>
<DT><B>Fukami, K. </B>
<DD><A HREF="aspabs.htm#01a_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I>A Co-evaluation of FPGA Architectures and the CAD System for
Telecommunication</I></A>
<DT><B>Fukui, M. </B>
<DD><A HREF="aspabs.htm#08c_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> A 2-Dimensional Transistor Placement for Cell Synthesis</I></A>
<DT><B>Fummi, F. </B>
<DD><A HREF="aspabs.htm#05b_4"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> The Use of Hierarchical Information to Test Large Controllers</I></A>
</DL>
<HR>
<DL><H1><A NAME="G">G</A></H1>
<DT><B>Gajski, D. D. </B>
<DD><A HREF="aspabs.htm#keynote2"><IMG SRC="../../../../absicon.gif"></A>
<I> RT Level Power Analysis</I></A>
<DD><A HREF="aspabs.htm#04a_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> A Quantitative Analysis for Optimizing Memory Allocation</I></A>
<DD><A HREF="aspabs.htm#08a_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> RT Level Power Analysis</I></A>
<DT><B>Ganz, A. </B>
<DD><A HREF="aspabs.htm#06b_3"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
<A HREF="order.htm">
<I> Reducing the Complexity of Path Classification by Reconvergence Analysis</I></A>
<DT><B>Gerber, S. </B>
<DD><A HREF="aspabs.htm#08b_1"><IMG SRC="../../../../absicon.gif"></A>
<A HREF="order.htm"><IMG SRC="../../../../pdficon.gif"></A>
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<I> AND/OR Reasoning Graphs for Determining Prime Implicants in
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<DT><B>Hachiya, K. </B>
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<I> Low-Power Multiple-Valued Current-Mode Integrated Circuit with
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<DT><B>Hayashi, T. </B>
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<I> An Enhanced Iterative Improvement Method for Evaluating the Maximum
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<DT><B>Hayashi, T. </B>
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<I>A Co-evaluation of FPGA Architectures and the CAD System for
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<I> A Transformational Codesign Methodology</I></A>
<DT><B>Henftling, M. </B>
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<I> Reducing the Complexity of Path Classification by Reconvergence Analysis</I>
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<DT><B>Hillawi, J. </B>
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<I> Choosing a Digital Simulator</I></A>
<DT><B>Hiramine, M. </B>
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<I> A Rapid Prototyping Method for Top-Down Design of System-on-Chip
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<DT><B>Hirata, T. </B>
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<DT><B>Hirose, F. </B>
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<I> Acceleration of Mincut Partitioning using Hardware CAD Accelerator
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<I>VLSI Design and Education Center (VDEC) Current Status and future plan
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<DT><B>Hong, H.-C. </B>
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<I> Analysis and Design of Multiple-Bit High-Order E-^ Modulator</I></A>
<DT><B>Hong, S.K. </B>
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<I> HK386: An x86-Compatible 32bit CICS Microprocessor</I></A>
<DT><B>Hong, Y.-S. </B>
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<I> A Quantitative Analysis for Optimizing Memory Allocation</I></A>
<DT><B>Hsieh, C. </B>
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<I> Statistical Design of Macro-models For RT-level Power Evaluation</I></A>
<DT><B>Hsu, Y.-C. </B>
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<I> On the Share-routine Implementation of Subprogram Synthesis</I></A>
<DT><B>Huang, I.-J. </B>
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<I> Synthesis and Analysis of an Industrial Embedded Microcontroller</I></A>
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<I> BDD Based Lambda Set Selection in Roth-Karp Decomposition for LUT
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<I> AQUILA: An Equivalence Verifier for Large Sequential Circuits</I></A>
<DT><B>Hwang, C.-H. </B>
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<DT><B>Hwang, C.-T. </B>
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<I> On the Share-routine Implementation of Subprogram Synthesis</I></A>
<DT><B>Hwang, J.-S. </B>
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<I>Multi-Project Chip Service for University and Industry in Taiwan</I></A>
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<DT><B>Iguchi, Y. </B>
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<DT><B>Iida, T. </B>
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<DT><B>Imai, M. </B>
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<I> VLSI Implementation of a Real-time Operating System</I> </A>
<DT><B>Ing, W.-L. </B>
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<DT><B>Inoue, M. </B>
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<I> Non-Scan Design for Testable Data Paths Using Thru Operation</I></A>
<DT><B>Iso, N. </B>
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<DT><B>Ito, K. </B>
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<I> Structural Approach for Performance Driven ECC Circuit Synthesis</I></A>
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<I> HK386: An x86-Compatible 32bit CICS Microprocessor</I></A>
<DT><B>Kim, N.H. </B><BR>
<DD><I> Interconnect Capacitances, Crosstalk, and Signal Delay in High Speed
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<DT><B>Kim, T.-H. </B>
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<I> Embedded Architectural Simulation within Behavioral Synthesis Environment</I></A>
<DT><B>Kita, H. </B>
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<DT><B>Kunieda, H. </B>
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<I> AND/OR Reasoning Graphs for Determining Prime Implicants in
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<I> On Synthesis of Speed-Independent Circuits at STG Level</I></A>
<DT><B>Kuo, M.-T. </B>
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<I> BDD-based Logic Partitioning for Sequential Circuits</I></A>
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<DT><B>Kyung, C.-M. </B>
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<I>Multi-Project Chip Activities in Korea-IDEC Perspective-</I></A>
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<DT><B>Landwehr, B. </B>
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<I> Built-in Chaining: Introducing Complex Components into Architectural
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<DT><B>Lavagno, L. </B>
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<I> Trade-off Evaluation in Embedded System Design Via Co-simulation</I></A>
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<I> Super Low Power 8-bit CPU with Pass-Transistor Logic</I></A>
<DT><B>Lee, G. </B>
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<I> Logic Synthesis for Cellular Architecture FPGAs Using BDDs</I></A>
<DT><B>Lee, H.-C. </B>
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<I> Verification Methodology of Compatible Microprocessors</I></A>
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<I> Single Cycle Access Cache for the Misaligned Data and Instruction Prefetch</I></A>
<DT><B>Lee, M. T.-C. </B>
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<I> On the Share-routine Implementation of Subprogram Synthesis</I></A>
<DT><B>Lee, S.-J. </B>
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<I> Verification Methodology of Compatible Microprocessors</I></A>
<DT><B>Lee, S.J. </B>
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<DT><B>Lee, Y.-H. </B>
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<I> Verification Methodology of Compatible Microprocessors</I></A>
<DT><B>Lee, Y.S. </B>
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<DT><B>Li, S. C. </B>
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<I> +-1.5V CMOS Four-Quardrant Multiplier</I></A>
<DT><B>Lillis, J. </B>
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<I> Optimal Loop Bandwidth Design for Low Noise PLL Applications</I></A>
<DT><B>Lin, B.-H. </B>
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<I> Analysis and Design of Multiple-Bit High-Order E-^ Modulator</I></A>
<DT><B>Lin, J.-Y. </B>
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<I> CB-Power: A Hierarchical Cell-Based Power Characterization and Estimation
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<I> An Improved Objective for Cell Placement</I></A>
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<I> A New Layout-Driven Timing Model for Incremental Layout Optimization</I></A>
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<I> CB-Power: A Hierarchical Cell-Based Power Characterization and Estimation
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<DT><B>Maeng, S.R. </B>
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<DT><B>Naganuma, J. </B>
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<DT><B>Okino, K. </B>
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Delay Model for Row Based VLSIs</I></A>
<DT><B>Onodera, H. </B>
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<I> A Current Mode Cyclic A/D Converter with a 0.8um CMOS Process</I></A>
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<I> A Rapid Prototyping Method for Top-Down Design of System-on-Chip
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<DT><B>Pang, J.T.C. </B>
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<I> Self-Timed 1-D ICT Processor</I></A>
<DT><B>Parameswaran, S. </B>
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<I> Power Consumption in CMOS Combinational Logic Blocks at High
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<DT><B>Park, B.-I., </B>
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<I> Single Cycle Access Cache for the Misaligned Data and Instruction Prefetch</I></A>
<DT><B>Park, C.-J. </B>
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<I> Verification Methodology of Compatible Microprocessors</I></A>
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<I> Single Cycle Access Cache for the Misaligned Data and Instruction Prefetch</I></A>
<DT><B>Park, H.S. </B><BR>
<DD><I> Interconnect Capacitances, Crosstalk, and Signal Delay in High Speed
and High Density VLSI Circuits (No Paper Submitted) </I>
<DT><B>Park, I.-C. </B>
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<I> Verification Methodology of Compatible Microprocessors</I></A>
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<I> HK386: An x86-Compatible 32bit CICS Microprocessor</I></A>
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<I> Single Cycle Access Cache for the Misaligned Data and Instruction Prefetch</I></A>
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<I>Multi-Project Chip Activities in Korea-IDEC Perspective-</I></A>
<DT><B>Park, J.-H. </B>
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<I> Performance Test of Viterbi Decoder for Wideband CDMA System</I></A>
<DT><B>Park, S.H. </B>
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<I> HK386: An x86-Compatible 32bit CICS Microprocessor</I></A>
<DT><B>Passerone, C. </B>
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<I> Trade-off Evaluation in Embedded System Design Via Co-simulation</I></A>
<DT><B>Pedram, M. </B>
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<I> A Note on the Relationship Between Signal Probability and Switching
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<I> Adaptive Models for Input Data Compaction for Power Simulators</I></A>
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<I> Statistical Design of Macro-models For RT-level Power Evaluation</I></A>
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<I> A New Description of CMOS Circuits at Switch-Level</I></A>
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<DT><B>Rao, L. </B>
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<I> Parallel Calculation of 3-D Parasitic Resistance and Capacitance
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<DT><B>Rho, Y.-C. </B>
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<I> Performance Test of Viterbi Decoder for Wideband CDMA System</I></A>
<DT><B>Roy, K. </B>
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<I> Statistical Estimation of Combinational and Sequential CMOS Digital Circuit Activity Considering Uncertainty of Gate
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<I> Efficient Synthesis of AND/XOR Networks</I></A>
<DT><B>Roychowdhury, J.S. </B>
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<I> A New Linear-Time Harmonic Balance Algorithm for Cyclostationary
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<DT><B>Saika, S. </B>
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<I> A 2-Dimensional Transistor Placement for Cell Synthesis</I></A>
<DT><B>Saito, K. </B>
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<I> Advanced Processor Design using Hardware Description Language AIDL</I></A>
<DT><B>Saito, T. </B>
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<I> Enhancement of Parallelism for Tearing-based Circuit Simulation</I></A>
<DT><B>Sakurai, R. </B>
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<I> A Testability Analysis Method for Register-Transfer Level Descriptions
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<DT><B>Sangiovanni-Vincentelli, A. </B>
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<I> Trade-off Evaluation in Embedded System Design Via Co-simulation</I></A>
<DT><B>Sano, M. </B>
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<I> Acceleration of Mincut Partitioning using Hardware CAD Accelerator
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<DT><B>Sansoe, C. </B>
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<I> Trade-off Evaluation in Embedded System Design Via Co-simulation</I></A>
<DT><B>Sarrafzadeh, M. </B>
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<I> Cube-Embedding Based State Encoding for Low Power Design</I></A>
<DT><B>Sasahara, M. </B>
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<I> An LSI Implementation of the Simple Serial Synchronized Multistage
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<DT><B>Sasao, T. </B>
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<I> On Properties of Kleene TDDs</I></A>
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<I> An Optimization of AND-OR-EXOR Three-level Networks</I></A>
<DT><B>Sato, M. </B>
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<I> A Simultaneous Placement and Global Routing Algorithm with Path
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<DT><B>Schrage, J. </B>
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<I> Modelling and Detection of Dynamic Errors due to Reflection - and
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<DT><B>Sciuto, D. </B>
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<I> The Use of Hierarchical Information to Test Large Controllers</I></A>
<DT><B>Seo, K. </B>
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<I> A Rapid Prototyping Method for Top-Down Design of System-on-Chip
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<DT><B>Seong, K.S. </B>
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<I> CBLO: A Clustering Based Linear Ordering Algorithm for Netlist
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<I> HK386: An x86-Compatible 32bit CICS Microprocessor</I></A>
<DT><B>Seung, M.H. </B><BR>
<DD><I> Interconnect Capacitances, Crosstalk, and Signal Delay in High Speed
and High Density VLSI Circuits (No Paper Submitted)</I>
<DT><B>Shen, W.-Z. </B>
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<I> CB-Power: A Hierarchical Cell-Based Power Characterization and Estimation
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<DT><B>Shi, C.-J. R. </B>
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<I> Block-Level Fault Isolation Using Partition Theory and Logic Minimization
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<I> Solving Constrained Via Minimization by Compact Linear Programming</I></A>
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<I> High Speed Bit-Serial Parallel Processing on Array Architecture</I></A>
<DT><B>Shimogori, S. </B>
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<I> Acceleration of Mincut Partitioning using Hardware CAD Accelerator
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<DT><B>Shinomiya, N. </B>
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<I> A 2-Dimensional Transistor Placement for Cell Synthesis</I></A>
<DT><B>Shiomi, A. </B>
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<I> VLSI Implementation of a Real-time Operating System</I> </A>
<DT><B>Shirakawa, I. </B>
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<I> A High Performance FIR Filter Dedicated to Digital Video Transmission
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<DT><B>Song, H.-J. </B>
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<I>Multi-Project Chip Activities in Korea-IDEC Perspective-</I></A>
<DT><B>Stoffel, D. </B>
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<I> AND/OR Reasoning Graphs for Determining Prime Implicants in
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<DT><B>Su, C. </B>
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<I> Structural Approach for Performance Driven ECC Circuit Synthesis</I></A>
<DT><B>Su, H.-P. </B>
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<I> An Improved Objective for Cell Placement</I></A>
<DT><B>Su, M. </B>
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<I> VIDE: A Visual VHDL Integrated Design Environment</I></A>
<DT><B>Suen, A.-N. </B>
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<I> A Programmable Application-Specific VLSI Architecture and Implementation
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<DT><B>Sugimoto, Y. </B>
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<I> A Current-mode,3V,20MHz, 9-bit equivalent CMOS Sample-and-Hold
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<DT><B>Suzuki, F. </B>
<DD><A HREF="aspabs.htm#01a_2"><IMG SRC="../../../../absicon.gif"></A>
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<I> A Rapid Prototyping Method for Top-Down Design of System-on-Chip
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<DT><B>Tafat, A. </B>
<DD><A HREF="aspabs.htm#03c_3"><IMG SRC="../../../../absicon.gif"></A>
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<I> A New Approach for an AHDL Based on System Semantics</I></A>
<DT><B>Tafertshofer, P. </B>
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<I> Reducing the Complexity of Path Classification by Reconvergence Analysis</I></A>
<DT><B>Takabatake, K. </B>
<DD><A HREF="aspabs.htm#05b_2"><IMG SRC="../../../../absicon.gif"></A>
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<I> Non-Scan Design for Testable Data Paths Using Thru Operation</I></A>
<DT><B>Takahara, A. </B>
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<I>A Co-evaluation of FPGA Architectures and the CAD System for
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<DT><B>Takahashi, A. </B>
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<I> Performance and Reliability Driven Clock Scheduling of Sequential Logic
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<DT><B>Takahashi, M. </B>
<DD><A HREF="aspabs.htm#05b_1"><IMG SRC="../../../../absicon.gif"></A>
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<I> A Testability Analysis Method for Register-Transfer Level Descriptions
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<DT><B>Takase, H. </B>
<DD><A HREF="aspabs.htm#02b_3"><IMG SRC="../../../../absicon.gif"></A>
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<I> An Enhanced Iterative Improvement Method for Evaluating the Maximum
Number of Simultaneous Switching Gates for Combinational Circuits</I></A>
<DT><B>Takeuchi, M. </B>
<DD><A HREF="aspabs.htm#04d_03"><IMG SRC="../../../../absicon.gif"></A>
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<I> A Functional Memory Type Parallel Processor for Vector Quantization</I></A>
<DT><B>Takeuchi, S. </B>
<DD><A HREF="aspabs.htm#02a_2"><IMG SRC="../../../../absicon.gif"></A>
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<I> A High Performance FIR Filter Dedicated to Digital Video Transmission
</I></A>
<DT><B>Taki, K. </B>
<DD><A HREF="aspabs.htm#04d_02"><IMG SRC="../../../../absicon.gif"></A>
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<I> Super Low Power 8-bit CPU with Pass-Transistor Logic</I></A>
<DT><B>Tamaru, K. </B>
<DD><A HREF="aspabs.htm#04d_03"><IMG SRC="../../../../absicon.gif"></A>
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<I> A Functional Memory Type Parallel Processor for Vector Quantization</I></A>
<DD><A HREF="aspabs.htm#04d_12"><IMG SRC="../../../../absicon.gif"></A>
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<I> A Current Mode Cyclic A/D Converter with a 0.8um CMOS Process</I></A>
<DT><B>Tamiya, Y. </B>
<DD><A HREF="aspabs.htm#01b_2"><IMG SRC="../../../../absicon.gif"></A>
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<I> Delay Estimation for Technology Independent Synthesis</I></A>
<DT><B>Tanabe, N. </B>
<DD><A HREF="aspabs.htm#07c_3"><IMG SRC="../../../../absicon.gif"></A>
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<I> Enhancement of Parallelism for Tearing-based Circuit Simulation</I></A>
<DT><B>Tanaka, H. </B>
<DD><A HREF="aspabs.htm#04d_02"><IMG SRC="../../../../absicon.gif"></A>
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<I> Super Low Power 8-bit CPU with Pass-Transistor Logic</I></A>
<DT><B>Taniguchi, K. </B>
<DD><A HREF="aspabs.htm#05c_2"><IMG SRC="../../../../absicon.gif"></A>
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<I> Monte Carlo Simulation for Single Electron Circuits</I></A>
<DT><B>Tanimoto, H. </B>
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<I> A Time-Domain Method for Numerical Noise Analysis of Oscillators</I></A>
<DT><B>Tian, J. </B>
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<I> Concurrent Cell Generation and Mapping for CMOS Logic Circuits</I></A>
<DT><B>Tianming, K. </B>
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<I> VEAP: Global Optimization based Efficient Algorithm for VLSI Placement</I></A>
<DT><B>Togawa, N. </B>
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<I> A Simultaneous Placement and Global Routing Algorithm with Path
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<I> Design Driven Partitioning</I></A>
<DT><B>Tsay, Y.-W. </B>
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